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| author | Jannis Harder <me@jix.one> | 2022-11-10 16:17:54 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-11-30 18:24:35 +0100 |
| commit | b982ab4f59298946021186403e6415ba79e59200 (patch) | |
| tree | 6b7468718566b6374526637a8556a2b753c6253f /techlibs | |
| parent | 1e67c3a3c2455b6c15f6366d16406cd964001a07 (diff) | |
| download | yosys-b982ab4f59298946021186403e6415ba79e59200.tar.gz yosys-b982ab4f59298946021186403e6415ba79e59200.tar.bz2 yosys-b982ab4f59298946021186403e6415ba79e59200.zip | |
satgen, simlib: Consistent x-propagation for `$pmux` cells
This updates satgen and simlib to use a `$pmux` model where the output
is fully X when the S input is not all zero or one-hot with no x bits.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/simlib.v | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index e64697efb..b5e437d90 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1331,10 +1331,17 @@ always @* begin Y = A; found_active_sel_bit = 0; for (i = 0; i < S_WIDTH; i = i+1) - if (S[i]) begin - Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i); - found_active_sel_bit = 1; - end + case (S[i]) + 1'b1: begin + Y = found_active_sel_bit ? 'bx : B >> (WIDTH*i); + found_active_sel_bit = 1; + end + 1'b0: ; + 1'bx: begin + Y = 'bx; + found_active_sel_bit = 'bx; + end + endcase end endmodule |