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author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-28 09:06:37 -0700 |
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committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-28 14:25:46 -0700 |
commit | c3145863e7a815f60b62b8d015506672ccdbcd89 (patch) | |
tree | 256e22be275cc925a6f8e36c862960de9bbd63dd /techlibs | |
parent | 393b18e8e17432349797a1f228a7ddc7e2f7a16c (diff) | |
download | yosys-c3145863e7a815f60b62b8d015506672ccdbcd89.tar.gz yosys-c3145863e7a815f60b62b8d015506672ccdbcd89.tar.bz2 yosys-c3145863e7a815f60b62b8d015506672ccdbcd89.zip |
Reformatted GP_COUNTx_ADV resets to avoid Yosys thinking that they're multi-edge-sensitive and getting confused.
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 043cd18d4..b87795ceb 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, "RISING": begin always @(posedge CLK, posedge RST) begin - if(KEEP) begin + //Resets + if(RST) begin + if(RESET_VALUE == "ZERO") + count <= 0; + else + count <= COUNT_TO; + end + + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end + end + end + + "FALLING": begin + always @(posedge CLK, negedge RST) begin + //Resets - if(RST) begin + if(!RST) begin if(RESET_VALUE == "ZERO") count <= 0; else count <= COUNT_TO; end - end - end - - "FALLING": begin - always @(posedge CLK, negedge RST) begin - - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end - //Resets - if(!RST) begin - if(RESET_VALUE == "ZERO") - count <= 0; - else - count <= COUNT_TO; - end - end end @@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, "RISING": begin always @(posedge CLK, posedge RST) begin + //Resets + if(RST) begin + if(RESET_VALUE == "ZERO") + count <= 0; + else + count <= COUNT_TO; + end + //Main counter - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end + end + end + + "FALLING": begin + always @(posedge CLK, negedge RST) begin + //Resets - if(RST) begin + if(!RST) begin if(RESET_VALUE == "ZERO") count <= 0; else count <= COUNT_TO; end - end - end - - "FALLING": begin - always @(posedge CLK, negedge RST) begin - //Main counter - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end - //Resets - if(!RST) begin - if(RESET_VALUE == "ZERO") - count <= 0; - else - count <= COUNT_TO; - end - end end |