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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-20 13:03:48 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-20 13:03:48 -0800 |
| commit | e58c3f8351763facc12f61c42797cc2a5edf0907 (patch) | |
| tree | 3332182623313ac4aedc9c28adf4deb3a6fc70d6 /techlibs | |
| parent | 319cba70d37eafdb8bbd3ddf6a0f9c238d53d0c2 (diff) | |
| parent | 10e82e103f7b95d5a50d2ac85bc8e07e4461e388 (diff) | |
| download | yosys-e58c3f8351763facc12f61c42797cc2a5edf0907.tar.gz yosys-e58c3f8351763facc12f61c42797cc2a5edf0907.tar.bz2 yosys-e58c3f8351763facc12f61c42797cc2a5edf0907.zip | |
Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup
Revert "Optimise write_xaiger"
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 5 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 5 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 5 |
3 files changed, 0 insertions, 15 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 16ff9c57a..b71bb2395 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -321,11 +321,6 @@ struct SynthEcp5Pass : public ScriptPass run("techmap " + techmap_args); if (abc9) { - run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); - run("wbflip @abc9_boxes"); - run("techmap -autoproc @abc9_boxes"); - run("aigmap @abc9_boxes"); - run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 5073ba917..ed7a16c08 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -350,11 +350,6 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { - run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); - run("wbflip @abc9_boxes"); - run("techmap -autoproc @abc9_boxes"); - run("aigmap @abc9_boxes"); - run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/ice40/abc9_model.v"); int wire_delay; if (device_opt == "lp") diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ff530b819..971089b28 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -540,11 +540,6 @@ struct SynthXilinxPass : public ScriptPass log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); run("techmap -map +/xilinx/abc9_map.v -max_iter 1"); - run("select -set abc9_boxes A:abc9_box_id A:whitebox=1"); - run("wbflip @abc9_boxes"); - run("techmap -autoproc @abc9_boxes"); - run("aigmap @abc9_boxes"); - run("wbflip @abc9_boxes"); run("read_verilog -icells -lib +/xilinx/abc9_model.v"); std::string abc9_opts = " -box +/xilinx/abc9_xc7.box"; abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY); |