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| author | whitequark <whitequark@whitequark.org> | 2020-02-06 16:22:22 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-02-06 16:22:42 +0000 |
| commit | e95a8ba763999b9cce480a3aadf9fae206650f00 (patch) | |
| tree | 6fbe88d0c6614f26dca9e8dcfeffbe5bd8caf91b /techlibs | |
| parent | d44848328b329489eda0719968c3f81d4d9a6b55 (diff) | |
| download | yosys-e95a8ba763999b9cce480a3aadf9fae206650f00.tar.gz yosys-e95a8ba763999b9cce480a3aadf9fae206650f00.tar.bz2 yosys-e95a8ba763999b9cce480a3aadf9fae206650f00.zip | |
write_verilog: dump $mem cell attributes.
The Verilog backend already dumps attributes on RTLIL::Memory objects
but not on `$mem` cells.
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions