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| author | William D. Jones <thor0505@comcast.net> | 2020-11-26 18:47:11 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | f07b8eb606e9bcbf425510d938145a1e30e54b5d (patch) | |
| tree | eaba0ee2d83f8a79107a15183c3579b7ac59ab18 /techlibs | |
| parent | c76f361b56216aa4021c88e5d00b7d8323165967 (diff) | |
| download | yosys-f07b8eb606e9bcbf425510d938145a1e30e54b5d.tar.gz yosys-f07b8eb606e9bcbf425510d938145a1e30e54b5d.tar.bz2 yosys-f07b8eb606e9bcbf425510d938145a1e30e54b5d.zip | |
machxo2: Fix cells_sim typo where OFX1 was multiply-driven.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index ef40f0231..1cb45650a 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -129,7 +129,7 @@ module FACADE_SLICE #( wire k0; wire k1; - PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX1)); + PFUMX K0K1MUX (.ALUT(k1), .BLUT(k0), .C0(M0), .Z(OFX0)); LUT4 #(.INIT(LUT0_INITVAL)) LUT_0 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k0)); LUT4 #(.INIT(LUT0_INITVAL)) LUT_1 (.A(A0), .B(B0), .C(C0), .D(D0), .Z(k1)); |