Revert "Remove sequential extension"

This reverts commit 091bf4a18b2f4bf84fe62b61577c88d961468b3c.

6 files changed, 359 insertions, 17 deletions

diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 121862692..a760b3d6d 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -20,6 +20,103 @@
 
 // ============================================================================
 
+module FDRE (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ ;
+  \$__ABC_FDRE_1 #(
+      .INIT(|0),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDCE_1 #(
+    .INIT(INIT),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+    .CLK_POLARITY(!IS_C_INVERTED),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b0;
+  wire \$nextQ , \$currQ ;
+  \$__ABC_FDPE_1 #(
+    .INIT(INIT),
+    .CLK_POLARITY(1'b0),
+    .EN_POLARITY(1'b1)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+  \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+  \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+
 module RAM32X1D (
   output DPO, SPO,
   input  D,
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index e3e9686b5..7162bd213 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -26,6 +26,94 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1);
                 : (S0 ? I1 : I0);
 endmodule
 
+module \$__ABC_FF_ (input C, D, output Q);
+endmodule
+
+(* abc_box_id = 1000 *)
+module \$__ABC_ASYNC (input A, S, output Y);
+endmodule
+
+(* abc_box_id=1001, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
+endmodule
+
+(* abc_box_id=1002, lib_whitebox, abc_flop *)
+module \$__ABC_FDRE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+endmodule
+
+(* abc_box_id=1003, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1004, lib_whitebox, abc_flop *)
+module \$__ABC_FDCE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !CLR) ? D : \$pastQ ;
+endmodule
+
+(* abc_box_id=1005, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE ((* abc_flop_q, abc_arrival=303 *) output Q,
+                     (* abc_flop_clk *) input C,
+                     (* abc_flop_en *)  input CE,
+                     (* abc_flop_d *)   input D,
+                     input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
+endmodule
+
+(* abc_box_id=1006, lib_whitebox, abc_flop *)
+module \$__ABC_FDPE_1 ((* abc_flop_q, abc_arrival=303 *) output Q,
+                       (* abc_flop_clk *) input C,
+                       (* abc_flop_en *)  input CE,
+                       (* abc_flop_d *)   input D,
+                       input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0; 
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = (CE && !PRE) ? D : \$pastQ ;
+endmodule
+
 (* abc_box_id=2000 *)
 module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
 endmodule
@@ -33,6 +121,7 @@ endmodule
 module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
 endmodule
 
+
 module \$__ABC_RAM32X1D (
   // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
   (* abc_arrival=1153 *) output DPO, SPO,
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index 779fc5aac..d00d27e2e 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -20,6 +20,125 @@
 
 // ============================================================================
 
+module \$__ABC_ASYNC (input A, S, output Y);
+  assign Y = A;
+endmodule
+
+module \$__ABC_FDRE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDRE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_R_INVERTED(IS_R_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+endmodule
+
+module \$__ABC_FDRE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input R, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+  assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
+
+  FDRE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .R(R)
+  );
+endmodule
+
+module \$__ABC_FDCE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDCE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_CLR_INVERTED(IS_CLR_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+endmodule
+
+module \$__ABC_FDCE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input CLR, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+
+  FDCE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .CLR(CLR)
+  );
+endmodule
+
+module \$__ABC_FDPE (output Q,
+                     input C,
+                     input CE,
+                     input D,
+                     input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter CLK_POLARITY = !IS_C_INVERTED;
+  parameter EN_POLARITY = 1'b1;
+
+  FDPE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_PRE_INVERTED(IS_PRE_INVERTED),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+endmodule
+
+module \$__ABC_FDPE_1 (output Q,
+                       input C,
+                       input CE,
+                       input D,
+                       input PRE, \$pastQ );
+  parameter [0:0] INIT = 1'b0;
+  parameter CLK_POLARITY = 1'b0;
+  parameter EN_POLARITY = 1'b1;
+
+  FDPE_1 #(
+    .INIT(INIT),
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .PRE(PRE)
+  );
+endmodule
+
 module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
   assign Y = A;
 endmodule
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box
index 61b89b8af..c08af6320 100644
--- a/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@ -38,6 +38,47 @@ CARRY4 4 1 10 8
 592 540 520 356 -   512 548 292 -   228
 580 526 507 398 385 508 528 378 380 114
 
+# Box to emulate async behaviour of FD[CP]*
+# Inputs: A S
+# Outputs: Y
+$__ABC_ASYNC 1000 0 2 1
+0 764
+
+# The following FD*.{CE,R,CLR,PRE) are offset by 46ps to
+# reflect the -46ps Tsu
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
+# https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L265-L277
+
+# Inputs: C CE D R \$pastQ
+# Outputs: Q
+FDRE 1001 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE D R \$pastQ
+# Outputs: Q
+FDRE_1 1002 1 5 1
+0 151 0 446 0
+
+# Inputs: C CE CLR D \$pastQ
+# Outputs: Q
+FDCE 1003 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE CLR D \$pastQ
+# Outputs: Q
+FDCE_1 1004 1 5 1
+0 151 806 0 0
+
+# Inputs: C CE D PRE \$pastQ
+# Outputs: Q
+FDPE 1005 1 5 1
+0 151 0 806 0
+
+# Inputs: C CE D PRE \$pastQ
+# Outputs: Q
+FDPE_1 1006 1 5 1
+0 151 0 806 0
+
 # SLICEM/A6LUT
 # Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
 # Inputs: A S0 S1 S2 S3 S4 S5
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index d879a56ee..1ab718ccc 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -211,8 +211,7 @@ endmodule
 
 `endif
 
-module FDRE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, R);
+module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -224,8 +223,7 @@ module FDRE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDSE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, S);
+module FDSE (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -237,8 +235,7 @@ module FDSE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDCE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, CLR);
+module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -252,8 +249,7 @@ module FDCE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDPE ((* abc_arrival=303 *) output reg Q,
-             input C, CE, D, PRE);
+module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   parameter [0:0] IS_C_INVERTED = 1'b0;
   parameter [0:0] IS_D_INVERTED = 1'b0;
@@ -267,29 +263,25 @@ module FDPE ((* abc_arrival=303 *) output reg Q,
   endcase endgenerate
 endmodule
 
-module FDRE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, R);
+module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
-module FDSE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, S);
+module FDSE_1 (output reg Q, input C, CE, D, S);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
-module FDCE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, CLR);
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   initial Q <= INIT;
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDPE_1 ((* abc_arrival=303 *) output reg Q,
-               input C, CE, D, PRE);
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b9c4df82f..d28cd2428 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -379,6 +379,8 @@ struct SynthXilinxPass : public ScriptPass
 			std::string techmap_args = "-map +/techmap.v -map +/xilinx/cells_map.v";
 			if (widemux > 0)
 				techmap_args += stringf(" -D MIN_MUX_INPUTS=%d", widemux);
+			if (abc9)
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("clean");
 		}
@@ -409,9 +411,11 @@ struct SynthXilinxPass : public ScriptPass
 			//   has performed any necessary retiming
 			if (!nosrl || help_mode)
 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
-			std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/ff_map.v";
+			std::string techmap_args = "-map +/xilinx/lut_map.v";
 			if (abc9)
 				techmap_args += " -map +/xilinx/abc_unmap.v";
+			else
+				techmap_args += " -map +/xilinx/ff_map.v";
 			run("techmap " + techmap_args);
 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");