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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 21:55:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 21:55:53 -0700 |
| commit | f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf (patch) | |
| tree | 0a2c68573d86d58b4acdcd0a5075171c0f48881a /techlibs | |
| parent | 1123c09588a6dd3964605de229c6bc4ac158b50e (diff) | |
| download | yosys-f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf.tar.gz yosys-f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf.tar.bz2 yosys-f6203e6bd65f7383f14a15e926fc4b8f5f9a3edf.zip | |
Missing endmodule
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc_model.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v index b302e46f6..8255804c2 100644 --- a/techlibs/xilinx/abc_model.v +++ b/techlibs/xilinx/abc_model.v @@ -35,6 +35,7 @@ endmodule (* abc_box_id = 1000 *) module \$__ABC_ASYNC (input A, S, output Y); +endmodule // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} // Necessary since RAMD* and SRL* have both combinatorial (i.e. |