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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-07 12:31:32 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-07 12:31:32 +0200 |
| commit | 48f7682e32a3aead82b304c3d13fa47920e128c0 (patch) | |
| tree | f0fbd11b7948d1cece0add7d82f580216e4fa439 /tests/aiger/false.aig | |
| parent | 4c49ddf36af217d0dfa7dbd9d7e24b4dbc388ba9 (diff) | |
| parent | 3b8c917025e1be9695468588082e9175e918c9e9 (diff) | |
| download | yosys-48f7682e32a3aead82b304c3d13fa47920e128c0.tar.gz yosys-48f7682e32a3aead82b304c3d13fa47920e128c0.tar.bz2 yosys-48f7682e32a3aead82b304c3d13fa47920e128c0.zip | |
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
Diffstat (limited to 'tests/aiger/false.aig')
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