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author | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-19 15:40:39 -0800 |
commit | 09ee96e8c22ec692ee3ee31b8c211646eabbcf27 (patch) | |
tree | 8b24dad9db0013ee3db20326b00941bd2abb10d1 /tests/arch/common/mux.v | |
parent | 304e5f9ea45b8a4e2a28aba7f2820d1862377fef (diff) | |
parent | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (diff) | |
download | yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.gz yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.tar.bz2 yosys-09ee96e8c22ec692ee3ee31b8c211646eabbcf27.zip |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'tests/arch/common/mux.v')
-rw-r--r-- | tests/arch/common/mux.v | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v new file mode 100644 index 000000000..71c1ac7f2 --- /dev/null +++ b/tests/arch/common/mux.v @@ -0,0 +1,60 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + input[1:0] S; + input[3:0] D; + output Y; + + reg Y; + wire[1:0] S; + wire[3:0] D; + + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase + end +endmodule + +module mux8 ( S, D, Y ); + input[2:0] S; + input[7:0] D; + output Y; + + reg Y; + wire[2:0] S; + wire[7:0] D; + + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase + end +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + + assign Y = D[S]; +endmodule |