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| author | Lofty <dan.ravensloft@gmail.com> | 2021-04-12 10:33:40 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-04-17 20:54:58 +0200 |
| commit | dce037a62c5bda9a8256d271d39b06be366120e8 (patch) | |
| tree | 67d022cbceb487f5359215d7c9ca51959100f549 /tests/arch/quicklogic/latches.ys | |
| parent | a58571d0fe8971cb7d3a619a31b2c21be6d75bac (diff) | |
| download | yosys-dce037a62c5bda9a8256d271d39b06be366120e8.tar.gz yosys-dce037a62c5bda9a8256d271d39b06be366120e8.tar.bz2 yosys-dce037a62c5bda9a8256d271d39b06be366120e8.zip | |
quicklogic: ABC9 synthesis
Diffstat (limited to 'tests/arch/quicklogic/latches.ys')
| -rw-r--r-- | tests/arch/quicklogic/latches.ys | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/latches.ys index d7652f749..bcef42990 100644 --- a/tests/arch/quicklogic/latches.ys +++ b/tests/arch/quicklogic/latches.ys @@ -32,8 +32,9 @@ proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_quicklogic cd latchsr # Constrain all select calls below inside the top module -select -assert-count 2 t:LUT3 +select -assert-count 1 t:LUT2 +select -assert-count 1 t:LUT4 select -assert-count 5 t:inpad select -assert-count 1 t:outpad -select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D +select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D |