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-rw-r--r--tests/arch/quicklogic/latches.ys5
1 files changed, 3 insertions, 2 deletions
diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/latches.ys
index d7652f749..bcef42990 100644
--- a/tests/arch/quicklogic/latches.ys
+++ b/tests/arch/quicklogic/latches.ys
@@ -32,8 +32,9 @@ proc
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic
cd latchsr # Constrain all select calls below inside the top module
-select -assert-count 2 t:LUT3
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:LUT4
select -assert-count 5 t:inpad
select -assert-count 1 t:outpad
-select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D
+select -assert-none t:LUT2 t:LUT4 t:inpad t:outpad %% t:* %D