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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-19 09:31:17 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-01-19 09:31:17 +0100 |
| commit | c4b61f2d69e88ddefd8ceec02ccf074c1b713004 (patch) | |
| tree | 782154b88c14c839bd7640fd144d16f94a594062 /tests/asicworld/code_hdl_models_misc1.v | |
| parent | f3556e9f7ac6947be440a51699af773655de4911 (diff) | |
| parent | 95b6c3588222564b86cfa73f0601be44e3af5786 (diff) | |
| download | yosys-c4b61f2d69e88ddefd8ceec02ccf074c1b713004.tar.gz yosys-c4b61f2d69e88ddefd8ceec02ccf074c1b713004.tar.bz2 yosys-c4b61f2d69e88ddefd8ceec02ccf074c1b713004.zip | |
Merge pull request #793 from whitequark/proc_clean_fix_fully_def
proc_clean: fix fully def check to consider compare/signal length
Diffstat (limited to 'tests/asicworld/code_hdl_models_misc1.v')
0 files changed, 0 insertions, 0 deletions