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| author | luke whittlesey <luke.whittlesey@gmail.com> | 2015-06-08 17:35:40 -0400 |
|---|---|---|
| committer | luke whittlesey <luke.whittlesey@gmail.com> | 2015-06-08 17:35:40 -0400 |
| commit | 2f90499e3db061e07fbe6cc544d7f888db34eb6d (patch) | |
| tree | 9af4a1d67252be260d214c858e215570169dd890 /tests/bram/run-single.sh | |
| parent | a8fe0409062cb214d61d527ad2060c1f3d585026 (diff) | |
| download | yosys-2f90499e3db061e07fbe6cc544d7f888db34eb6d.tar.gz yosys-2f90499e3db061e07fbe6cc544d7f888db34eb6d.tar.bz2 yosys-2f90499e3db061e07fbe6cc544d7f888db34eb6d.zip | |
$mem cell in verilog backend : grouped writes by clock
Diffstat (limited to 'tests/bram/run-single.sh')
| -rw-r--r-- | tests/bram/run-single.sh | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index a1d1ec908..19a235c7a 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,9 +1,7 @@ #!/bin/bash set -e -../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full; write_verilog temp/synth_${1}_${2}_stage0.v" \ - -l temp/synth_${1}_${2}_stage0.log temp/brams_${1}.v -../../yosys -qq -p "proc; opt; memory -nomap; opt -fast -full; write_verilog -nomem temp/synth_${1}_${2}.v" \ - -l temp/synth_${1}_${2}.log temp/synth_${1}_${2}_stage0.v +../../yosys -qq -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ + -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1ns -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt |