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| author | Clifford Wolf <clifford@clifford.at> | 2018-10-19 13:05:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-19 13:05:51 +0200 |
| commit | 2e32d05eabd1cf809fc01508be1951edad0680bf (patch) | |
| tree | 4d9ff9f35e8601deab89f31ef2a69405e8d6eb68 /tests/errors/syntax_err11.v | |
| parent | 2a104b29fd7e504bdedb27c286cf9125d46dfd55 (diff) | |
| parent | c7770d9eeaf9fba0c9d07e7cce020fe89ec71600 (diff) | |
| download | yosys-2e32d05eabd1cf809fc01508be1951edad0680bf.tar.gz yosys-2e32d05eabd1cf809fc01508be1951edad0680bf.tar.bz2 yosys-2e32d05eabd1cf809fc01508be1951edad0680bf.zip | |
Merge pull request #671 from rafaeltp/master
adding offset info to memories on verilog output
Diffstat (limited to 'tests/errors/syntax_err11.v')
0 files changed, 0 insertions, 0 deletions