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| author | Oliver Keszöcze <github@keszoecze.de> | 2023-02-17 17:54:41 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-17 17:54:41 +0100 |
| commit | fc56978703b5e942ba728970e13e065100a34cd7 (patch) | |
| tree | 5f6cca5a223055741e7041baf1181e68ebf4af96 /tests/gen-tests-makefile.sh | |
| parent | 1cfedc90ce7b2bd63d75883a4e8c36fd44f0e4e7 (diff) | |
| download | yosys-fc56978703b5e942ba728970e13e065100a34cd7.tar.gz yosys-fc56978703b5e942ba728970e13e065100a34cd7.tar.bz2 yosys-fc56978703b5e942ba728970e13e065100a34cd7.zip | |
Check DREG attribute
The DSP48E1 implementation checked the wrong attribute (i.e. CREG) to initialize the D input register. This PR fixes 3680
Diffstat (limited to 'tests/gen-tests-makefile.sh')
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