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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-05 09:16:35 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-05 09:16:35 -0800 |
| commit | 728a251a95d3c43d7fc6e439d0d9fbe6dac1bbc6 (patch) | |
| tree | c24ccc8fabbe0dbf74f00278900b866d7e6e0b32 /tests/lut/map_and.v | |
| parent | e1153031291275dc1c16445b1b2089ffd4335845 (diff) | |
| parent | d9fa4387c97745c558acdd8ea7f436917302796e (diff) | |
| download | yosys-728a251a95d3c43d7fc6e439d0d9fbe6dac1bbc6.tar.gz yosys-728a251a95d3c43d7fc6e439d0d9fbe6dac1bbc6.tar.bz2 yosys-728a251a95d3c43d7fc6e439d0d9fbe6dac1bbc6.zip | |
Merge pull request #718 from whitequark/gate2lut
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
Diffstat (limited to 'tests/lut/map_and.v')
| -rw-r--r-- | tests/lut/map_and.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/lut/map_and.v b/tests/lut/map_and.v new file mode 100644 index 000000000..68ae33fd6 --- /dev/null +++ b/tests/lut/map_and.v @@ -0,0 +1,5 @@ +module top(...); + input a, b; + output y; + assign y = a&b; +endmodule |