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| author | N. Engelhardt <nak@yosyshq.com> | 2023-02-20 18:27:24 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-20 18:27:24 +0100 |
| commit | c8966722d2fcbff67a2724f921a3692ab63d83ec (patch) | |
| tree | 28ebdac931b3e2614d8d82c9c3ec623b9e553dd5 /tests/memlib/memlib_lut.v | |
| parent | f0116330bce4e787dcbbf81c6e901a44715589a8 (diff) | |
| parent | f80920bd9f1b235693d61427d1532b8465fce12c (diff) | |
| download | yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.tar.gz yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.tar.bz2 yosys-c8966722d2fcbff67a2724f921a3692ab63d83ec.zip | |
Merge pull request #3403 from KrystalDelusion/mem-tests
Diffstat (limited to 'tests/memlib/memlib_lut.v')
| -rw-r--r-- | tests/memlib/memlib_lut.v | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/tests/memlib/memlib_lut.v b/tests/memlib/memlib_lut.v index 1f20a110a..2685d2337 100644 --- a/tests/memlib/memlib_lut.v +++ b/tests/memlib/memlib_lut.v @@ -9,6 +9,7 @@ module RAM_LUT( ); parameter INIT = 0; +parameter OPTION_INIT = "UNDEFINED"; parameter PORT_RW_CLK_POL = 1; reg [3:0] mem [0:15]; @@ -16,7 +17,13 @@ reg [3:0] mem [0:15]; integer i; initial for (i = 0; i < 16; i += 1) - mem[i] = INIT[i*4+:4]; + case (OPTION_INIT) + "NONE": mem[i] = mem[i]; //? + "ZERO": mem[i] = 4'h0; + "ANY": mem[i] = INIT[i*4+:4]; + "NO_UNDEF": mem[i] = INIT[i*4+:4]; + "UNDEFINED": mem[i] = 4'hx; + endcase assign PORT_R_RD_DATA = mem[PORT_R_ADDR]; assign PORT_RW_RD_DATA = mem[PORT_RW_ADDR]; |