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| author | Zachary Snow <zach@zachjs.com> | 2021-02-11 10:26:49 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-02-11 10:26:49 -0500 |
| commit | 73d611990d7f39b4e14ffc367c646686f0d2b209 (patch) | |
| tree | 6ed0d4b18195c987bef60a0134bf25514e4ab9ab /tests/simple/genblk_port_shadow.v | |
| parent | c383d156e9015cde4718f3a6bc3371dc87c3e4fe (diff) | |
| parent | 1d5f3fe5064146955dafdabafe7180ff79c95d08 (diff) | |
| download | yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.tar.gz yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.tar.bz2 yosys-73d611990d7f39b4e14ffc367c646686f0d2b209.zip | |
Merge pull request #2578 from zachjs/genblk-port
verlog: allow shadowing module ports within generate blocks
Diffstat (limited to 'tests/simple/genblk_port_shadow.v')
| -rw-r--r-- | tests/simple/genblk_port_shadow.v | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v new file mode 100644 index 000000000..a04631a20 --- /dev/null +++ b/tests/simple/genblk_port_shadow.v @@ -0,0 +1,10 @@ +module top(x); + generate + if (1) begin : blk + wire x; + assign x = 0; + end + endgenerate + output wire x; + assign x = blk.x; +endmodule |