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| author | Xiretza <xiretza@xiretza.xyz> | 2020-09-16 17:59:37 +0200 |
|---|---|---|
| committer | Xiretza <xiretza@xiretza.xyz> | 2020-09-21 15:07:02 +0200 |
| commit | acd47bbd52d11216b883b99f3e17ae4ffbd5f4a3 (patch) | |
| tree | df050fa4d1176a714b5c954f9d1d9f105ca61a61 /tests/techmap/mem_simple_4x1_runtest.sh | |
| parent | c6ff947f6bac336ab5a31913c2daf7ad1cb8b91b (diff) | |
| download | yosys-acd47bbd52d11216b883b99f3e17ae4ffbd5f4a3.tar.gz yosys-acd47bbd52d11216b883b99f3e17ae4ffbd5f4a3.tar.bz2 yosys-acd47bbd52d11216b883b99f3e17ae4ffbd5f4a3.zip | |
tests: Centralize test collection and Makefile generation
Diffstat (limited to 'tests/techmap/mem_simple_4x1_runtest.sh')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_runtest.sh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index e2c6303da..9c41fa56a 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -1,6 +1,6 @@ #!/bin/bash -set -ev +set -e ../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v |