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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-02 12:43:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-02 12:43:18 -0700 |
| commit | a4f2f7d23cb27f7677236d7a1823f36215c874e9 (patch) | |
| tree | 6c88067253e2a0cbf19350505dd4671d6ba75440 /tests/techmap/techmap_replace.ys | |
| parent | 369652d4b99181e2f7b875b6c458c1a5a3b0381e (diff) | |
| download | yosys-a4f2f7d23cb27f7677236d7a1823f36215c874e9.tar.gz yosys-a4f2f7d23cb27f7677236d7a1823f36215c874e9.tar.bz2 yosys-a4f2f7d23cb27f7677236d7a1823f36215c874e9.zip | |
Extend test with renaming cells with prefix too
Diffstat (limited to 'tests/techmap/techmap_replace.ys')
| -rw-r--r-- | tests/techmap/techmap_replace.ys | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys index ee5c6bc7e..c2f42d50b 100644 --- a/tests/techmap/techmap_replace.ys +++ b/tests/techmap/techmap_replace.ys @@ -2,6 +2,7 @@ read_verilog <<EOT module sub(input i, output o, input j); foobar _TECHMAP_REPLACE_(i, o, j); wire _TECHMAP_REPLACE_.asdf = i ; +barfoo _TECHMAP_REPLACE_.blah (i, o, j); endmodule EOT design -stash techmap @@ -14,3 +15,4 @@ EOT techmap -map %techmap select -assert-any w:s0.asdf +select -assert-any c:s0.blah |