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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:31:48 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 15:31:48 -0700 |
| commit | 1b08f861b6f95dba561ec48f71d3ab5bc18f64f2 (patch) | |
| tree | b08eebb56cfa49743504bfcb97d3778dedc13d9d /tests/xilinx/xilinx_srl.ys | |
| parent | 8d820a9884c0a58ee7817a2052d8b915578a7ba7 (diff) | |
| parent | 52c4655de32c027e0542834d030ac951be10c8eb (diff) | |
| download | yosys-1b08f861b6f95dba561ec48f71d3ab5bc18f64f2.tar.gz yosys-1b08f861b6f95dba561ec48f71d3ab5bc18f64f2.tar.bz2 yosys-1b08f861b6f95dba561ec48f71d3ab5bc18f64f2.zip | |
Merge branch 'eddie/xilinx_srl' into xaig_arrival
Diffstat (limited to 'tests/xilinx/xilinx_srl.ys')
| -rw-r--r-- | tests/xilinx/xilinx_srl.ys | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys new file mode 100644 index 000000000..b8df0e55a --- /dev/null +++ b/tests/xilinx/xilinx_srl.ys @@ -0,0 +1,67 @@ +read_verilog xilinx_srl.v +design -save read + +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_static_test +prep +design -save gold + +techmap +xilinx_srl -fixed +opt + +# stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +dump gate +sat -verify -prove-asserts -show-ports -seq 5 miter + +#design -load gold +#stat + +#design -load gate +#stat + +########## + +design -load read +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_variable_test +prep +design -save gold + +xilinx_srl -variable +opt + +#stat +# show -width +# write_verilog -noexpr -norename +select -assert-count 1 t:$dff +select -assert-count 1 t:$dff r:WIDTH=1 %i +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +# design -load gold +# stat + +# design -load gate +# stat |