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-rw-r--r--Makefile4
1 files changed, 4 insertions, 0 deletions
diff --git a/Makefile b/Makefile
index 4140c16f9..d1795f813 100644
--- a/Makefile
+++ b/Makefile
@@ -504,6 +504,10 @@ VERIFIC_COMPONENTS ?= verilog database util containers hier_tree
ifneq ($(DISABLE_VERIFIC_VHDL),1)
VERIFIC_COMPONENTS += vhdl
CXXFLAGS += -DVERIFIC_VHDL_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/vhdl),)
+VERIFIC_COMPONENTS += vhdl
+endif
endif
ifneq ($(DISABLE_VERIFIC_EXTENSIONS),1)
VERIFIC_COMPONENTS += extensions