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-rw-r--r--techlibs/ice40/cells_sim.v5
1 files changed, 0 insertions, 5 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index c7e4101e1..b746ba4e5 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -144,12 +144,8 @@ endmodule
// Positive Edge SiliconBlue FF Cells
module SB_DFF (output `SB_DFF_REG, input C, D);
-`ifndef _ABC
always @(posedge C)
Q <= D;
-`else
- always @* Q <= D;
-`endif
endmodule
module SB_DFFE (output `SB_DFF_REG, input C, E, D);
@@ -896,7 +892,6 @@ module SB_WARMBOOT (
);
endmodule
-(* nomem2reg *)
module SB_SPRAM256KA (
input [13:0] ADDRESS,
input [15:0] DATAIN,