1 files changed, 72 insertions, 1 deletions

diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v
index 3b4628675..5850f6907 100644
--- a/techlibs/intel_alm/common/quartus_rename.v
+++ b/techlibs/intel_alm/common/quartus_rename.v
@@ -2,11 +2,28 @@
 `define LCELL cyclonev_lcell_comb
 `define MAC cyclonev_mac
 `define MLAB cyclonev_mlab_cell
+`define RAM_BLOCK cyclonev_ram_block
+`define IBUF cyclonev_io_ibuf
+`define OBUF cyclonev_io_obuf
+`define CLKENA cyclonev_clkena
+`endif
+`ifdef arriav
+`define LCELL arriav_lcell_comb
+`define MAC arriav_mac
+`define MLAB arriav_mlab_cell
+`define RAM_BLOCK arriav_ram_block
+`define IBUF arriav_io_ibuf
+`define OBUF arriav_io_obuf
+`define CLKENA arriav_clkena
 `endif
 `ifdef cyclone10gx
 `define LCELL cyclone10gx_lcell_comb
 `define MAC cyclone10gx_mac
 `define MLAB cyclone10gx_mlab_cell
+`define RAM_BLOCK cyclone10gx_ram_block
+`define IBUF cyclone10gx_io_ibuf
+`define OBUF cyclone10gx_io_obuf
+`define CLKENA cyclone10gx_clkena
 `endif
 
 module __MISTRAL_VCC(output Q);
@@ -140,7 +157,7 @@ output [CFG_DBITS-1:0] B1DATA;
 // Much like the MLAB, the M10K has mem_init[01234] parameters which would let
 // you initialise the RAM cell via hex literals. If they were implemented.
 
-cyclonev_ram_block #(
+`RAM_BLOCK #(
     .operation_mode("dual_port"),
     .logical_ram_name(_TECHMAP_CELLNAME_),
     .port_a_address_width(CFG_ABITS),
@@ -233,3 +250,57 @@ parameter B_SIGNED = 1;
 );
 
 endmodule
+
+module MISTRAL_IB(input PAD, output O);
+`IBUF #(
+    .bus_hold("false"),
+    .differential_mode("false")
+) _TECHMAP_REPLACE_ (
+    .i(PAD),
+    .o(O)
+);
+endmodule
+
+module MISTRAL_OB(output PAD, input I, OE);
+`OBUF #(
+    .bus_hold("false"),
+    .differential_mode("false")
+) _TECHMAP_REPLACE_ (
+    .i(I),
+    .o(PAD),
+    .oe(OE)
+);
+endmodule
+
+module MISTRAL_IO(output PAD, input I, OE, output O);
+`IBUF #(
+    .bus_hold("false"),
+    .differential_mode("false")
+) ibuf (
+    .i(PAD),
+    .o(O)
+);
+
+`OBUF #(
+    .bus_hold("false"),
+    .differential_mode("false")
+) obuf (
+    .i(I),
+    .o(PAD),
+    .oe(OE)
+);
+endmodule
+
+module MISTRAL_CLKBUF (input A, output Q);
+`CLKENA #(
+    .clock_type("auto"),
+    .ena_register_mode("always enabled"),
+    .ena_register_power_up("high"),
+    .disable_mode("low"),
+    .test_syn("high")
+) _TECHMAP_REPLACE_ (
+    .inclk(A),
+    .ena(1'b1),
+    .outclk(Q)
+);
+endmodule