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-rw-r--r--techlibs/common/prep.cc6
-rw-r--r--techlibs/common/simlib.v176
-rw-r--r--techlibs/common/synth.cc2
-rw-r--r--techlibs/ecp5/cells_map.v15
-rw-r--r--techlibs/ecp5/synth_ecp5.cc2
-rw-r--r--techlibs/ice40/cells_sim.v35
-rw-r--r--techlibs/ice40/synth_ice40.cc12
-rw-r--r--techlibs/intel/synth_intel.cc433
-rw-r--r--techlibs/xilinx/cells_map.v10
-rw-r--r--techlibs/xilinx/drams.txt4
-rw-r--r--techlibs/xilinx/ff_map.v13
-rw-r--r--techlibs/xilinx/synth_xilinx.cc322
12 files changed, 624 insertions, 406 deletions
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index 86fb4d6c6..cdd21c3b3 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -195,9 +195,11 @@ struct PrepPass : public ScriptPass
run(nokeepdc ? "opt" : "opt -keepdc");
if (!ifxmode) {
if (help_mode)
- run("wreduce [-memx]");
- else
+ run("wreduce -keepdc [-memx]");
+ else if (nokeepdc)
run(memxmode ? "wreduce -memx" : "wreduce");
+ else
+ run(memxmode ? "wreduce -keepdc -memx" : "wreduce -keepdc");
}
if (!nomemmode) {
run(string("memory_dff") + (help_mode ? " [-nordff]" : nordff ? " -nordff" : ""));
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 8e43fe058..a424d3089 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1271,6 +1271,181 @@ endmodule
// --------------------------------------------------------
+module \$specify2 (EN, SRC, DST);
+
+parameter FULL = 0;
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_DST_PEN = 0;
+parameter SRC_DST_POL = 0;
+
+parameter T_RISE_MIN = 0;
+parameter T_RISE_TYP = 0;
+parameter T_RISE_MAX = 0;
+
+parameter T_FALL_MIN = 0;
+parameter T_FALL_TYP = 0;
+parameter T_FALL_MAX = 0;
+
+input EN;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
+
+`ifdef SIMLIB_SPECIFY
+specify
+ if (EN && SD==0 && !FULL) (SRC => DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==0 && FULL) (SRC *> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==1 && !FULL) (SRC +=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==1 && FULL) (SRC +*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==2 && !FULL) (SRC -=> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && SD==2 && FULL) (SRC -*> DST) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$specify3 (EN, SRC, DST, DAT);
+
+parameter FULL = 0;
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter EDGE_EN = 0;
+parameter EDGE_POL = 0;
+
+parameter SRC_DST_PEN = 0;
+parameter SRC_DST_POL = 0;
+
+parameter DAT_DST_PEN = 0;
+parameter DAT_DST_POL = 0;
+
+parameter T_RISE_MIN = 0;
+parameter T_RISE_TYP = 0;
+parameter T_RISE_MAX = 0;
+
+parameter T_FALL_MIN = 0;
+parameter T_FALL_TYP = 0;
+parameter T_FALL_MAX = 0;
+
+input EN;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST, DAT;
+
+localparam ED = EDGE_EN ? (EDGE_POL ? 1 : 2) : 0;
+localparam SD = SRC_DST_PEN ? (SRC_DST_POL ? 1 : 2) : 0;
+localparam DD = DAT_DST_PEN ? (DAT_DST_POL ? 1 : 2) : 0;
+
+`ifdef SIMLIB_SPECIFY
+specify
+ // DD=0
+
+ if (EN && DD==0 && SD==0 && ED==0 && !FULL) ( SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==0 && FULL) ( SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==0 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==0 && FULL) ( SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==0 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==0 && FULL) ( SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==0 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST : DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ // DD=1
+
+ if (EN && DD==1 && SD==0 && ED==0 && !FULL) ( SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==0 && FULL) ( SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==1 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==0 && FULL) ( SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==1 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==0 && FULL) ( SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==1 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST +: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ // DD=2
+
+ if (EN && DD==2 && SD==0 && ED==0 && !FULL) ( SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==0 && FULL) ( SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==1 && !FULL) (posedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==1 && FULL) (posedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==2 && !FULL) (negedge SRC => (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==0 && ED==2 && FULL) (negedge SRC *> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==2 && SD==1 && ED==0 && !FULL) ( SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==0 && FULL) ( SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==1 && !FULL) (posedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==1 && FULL) (posedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==2 && !FULL) (negedge SRC +=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==1 && ED==2 && FULL) (negedge SRC +*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+
+ if (EN && DD==2 && SD==2 && ED==0 && !FULL) ( SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==0 && FULL) ( SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==1 && !FULL) (posedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==1 && FULL) (posedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==2 && !FULL) (negedge SRC -=> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+ if (EN && DD==2 && SD==2 && ED==2 && FULL) (negedge SRC -*> (DST -: DAT)) = (T_RISE_MIN:T_RISE_TYP:T_RISE_MAX, T_FALL_MIN:T_FALL_TYP:T_FALL_MAX);
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$specrule (EN_SRC, EN_DST, SRC, DST);
+
+parameter TYPE = "";
+parameter T_LIMIT = 0;
+parameter T_LIMIT2 = 0;
+
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_PEN = 0;
+parameter SRC_POL = 0;
+
+parameter DST_PEN = 0;
+parameter DST_POL = 0;
+
+input EN_SRC, EN_DST;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+`ifdef SIMLIB_SPECIFY
+specify
+ // TBD
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
module \$assert (A, EN);
input A, EN;
@@ -1863,4 +2038,5 @@ end
endmodule
`endif
+
// --------------------------------------------------------
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 349605f8c..ee2e86de9 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -209,6 +209,8 @@ struct SynthPass : public ScriptPass
run("check");
run("opt");
run("wreduce");
+ run("peepopt");
+ run("opt_clean");
if (help_mode)
run("techmap -map +/cmp2lut.v", " (if -lut)");
else
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 6ab4b69f2..f6c71a03d 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,21 @@ module \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"
module \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
module \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+// Diamond I/O buffers
+module IB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPU (input I, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module IBPD (input I, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(I), .O(O)); endmodule
+module OB (input I, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I)); endmodule
+module OBZ (input I, T, output O); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPU(input I, T, output O); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBZPD(input I, T, output O); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(O), .I(I), .T(T)); endmodule
+module OBCO (input I, output OT, OC); OLVDS _TECHMAP_REPLACE_ (.A(I), .Z(OT), .ZN(OC)); endmodule
+module BB (input I, T, output O, inout B); (* PULLMODE="NONE" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPU (input I, T, output O, inout B); (* PULLMODE="UP" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module BBPD (input I, T, output O, inout B); (* PULLMODE="DOWN" *) TRELLIS_IO #(.DIR("BIDIR")) _TECHMAP_REPLACE_ (.B(B), .I(I), .O(O), .T(T)); endmodule
+module ILVDS(input A, AN, output Z); TRELLIS_IO #(.DIR("INPUT")) _TECHMAP_REPLACE_ (.B(A), .O(Z)); endmodule
+module OLVDS(input A, output Z, ZN); TRELLIS_IO #(.DIR("OUTPUT")) _TECHMAP_REPLACE_ (.B(Z), .I(A)); endmodule
+
// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4b889d672..c6e12248e 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -253,7 +253,7 @@ struct SynthEcp5Pass : public ScriptPass
if (!nodffe)
run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
- run("opt_expr -mux_undef");
+ run("opt_expr -undriven -mux_undef");
run("simplemap");
run("ecp5_ffinit");
}
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 40972766d..560008bc4 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -957,10 +957,21 @@ endmodule
(* blackbox *)
module SB_HFOSC(
+ input TRIM0,
+ input TRIM1,
+ input TRIM2,
+ input TRIM3,
+ input TRIM4,
+ input TRIM5,
+ input TRIM6,
+ input TRIM7,
+ input TRIM8,
+ input TRIM9,
input CLKHFPU,
input CLKHFEN,
output CLKHF
);
+parameter TRIM_EN = "0b0";
parameter CLKHF_DIV = "0b00";
endmodule
@@ -990,6 +1001,30 @@ parameter RGB2_CURRENT = "0b000000";
endmodule
(* blackbox *)
+module SB_LED_DRV_CUR(
+ input EN,
+ output LEDPU
+);
+endmodule
+
+(* blackbox *)
+module SB_RGB_DRV(
+ input RGBLEDEN,
+ input RGB0PWM,
+ input RGB1PWM,
+ input RGB2PWM,
+ input RGBPU,
+ output RGB0,
+ output RGB1,
+ output RGB2
+);
+parameter CURRENT_MODE = "0b0";
+parameter RGB0_CURRENT = "0b000000";
+parameter RGB1_CURRENT = "0b000000";
+parameter RGB2_CURRENT = "0b000000";
+endmodule
+
+(* blackbox *)
module SB_I2C(
input SBCLKI,
input SBRWI,
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 718f9d9e0..168161a90 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -245,11 +245,13 @@ struct SynthIce40Pass : public ScriptPass
run("proc");
}
- if (flatten && check_label("flatten", "(unless -noflatten)"))
+ if (check_label("flatten", "(unless -noflatten)"))
{
- run("flatten");
- run("tribuf -logic");
- run("deminout");
+ if (flatten) {
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
+ }
}
if (check_label("coarse"))
@@ -259,6 +261,8 @@ struct SynthIce40Pass : public ScriptPass
run("check");
run("opt");
run("wreduce");
+ run("peepopt");
+ run("opt_clean");
run("share");
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
run("opt_expr");
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index d2291b8d4..639cba2c2 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -17,254 +17,243 @@
*
*/
-#include "kernel/register.h"
#include "kernel/celltypes.h"
-#include "kernel/rtlil.h"
#include "kernel/log.h"
+#include "kernel/register.h"
+#include "kernel/rtlil.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct SynthIntelPass : public ScriptPass {
- SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { }
+ SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") {}
- void help() YS_OVERRIDE
- {
- // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
- log("\n");
- log(" synth_intel [options]\n");
- log("\n");
- log("This command runs synthesis for Intel FPGAs.\n");
- log("\n");
- log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
- log(" generate the synthesis netlist for the specified family.\n");
- log(" MAX10 is the default target if no family argument specified.\n");
- log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
- log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
- log("\n");
- log(" -top <module>\n");
- log(" use the specified module as top module (default='top')\n");
- log("\n");
- log(" -vqm <file>\n");
- log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
- log(" output file is omitted if this parameter is not specified.\n");
- log("\n");
- log(" -vpr <file>\n");
- log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
- log(" compatible with the Quartus flow. Writing of an\n");
- log(" output file is omitted if this parameter is not specified.\n");
- log("\n");
- log(" -run <from_label>:<to_label>\n");
- log(" only run the commands between the labels (see below). an empty\n");
- log(" from label is synonymous to 'begin', and empty to label is\n");
- log(" synonymous to the end of the command list.\n");
- log("\n");
- log(" -noiopads\n");
- log(" do not use altsyncram cells in output netlist\n");
- log("\n");
- log(" -nobram\n");
- log(" do not use altsyncram cells in output netlist\n");
- log("\n");
- log(" -noflatten\n");
- log(" do not flatten design before synthesis\n");
- log("\n");
- log(" -retime\n");
- log(" run 'abc' with -dff option\n");
- log("\n");
- log("The following commands are executed by this synthesis command:\n");
- help_script();
- log("\n");
- }
+ void help() YS_OVERRIDE
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" synth_intel [options]\n");
+ log("\n");
+ log("This command runs synthesis for Intel FPGAs.\n");
+ log("\n");
+ log(" -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>\n");
+ log(" generate the synthesis netlist for the specified family.\n");
+ log(" MAX10 is the default target if not family argument specified.\n");
+ log(" For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.\n");
+ log(" Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.\n");
+ log("\n");
+ log(" -top <module>\n");
+ log(" use the specified module as top module (default='top')\n");
+ log("\n");
+ log(" -vqm <file>\n");
+ log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n");
+ log(" output file is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -vpr <file>\n");
+ log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n");
+ log(" compatible with the Quartus flow. Writing of an\n");
+ log(" output file is omitted if this parameter is not specified.\n");
+ log("\n");
+ log(" -run <from_label>:<to_label>\n");
+ log(" only run the commands between the labels (see below). an empty\n");
+ log(" from label is synonymous to 'begin', and empty to label is\n");
+ log(" synonymous to the end of the command list.\n");
+ log("\n");
+ log(" -noiopads\n");
+ log(" do not use altsyncram cells in output netlist\n");
+ log("\n");
+ log(" -nobram\n");
+ log(" do not use altsyncram cells in output netlist\n");
+ log("\n");
+ log(" -noflatten\n");
+ log(" do not flatten design before synthesis\n");
+ log("\n");
+ log(" -retime\n");
+ log(" run 'abc' with -dff option\n");
+ log("\n");
+ log("The following commands are executed by this synthesis command:\n");
+ help_script();
+ log("\n");
+ }
- string top_opt, family_opt, vout_file, blif_file;
- bool retime, flatten, nobram, noiopads;
+ string top_opt, family_opt, vout_file, blif_file;
+ bool retime, flatten, nobram, noiopads;
- void clear_flags() YS_OVERRIDE
- {
- top_opt = "-auto-top";
- family_opt = "max10";
- vout_file = "";
- blif_file = "";
- retime = false;
- flatten = true;
- nobram = false;
- noiopads = false;
- }
+ void clear_flags() YS_OVERRIDE
+ {
+ top_opt = "-auto-top";
+ family_opt = "max10";
+ vout_file = "";
+ blif_file = "";
+ retime = false;
+ flatten = true;
+ nobram = false;
+ noiopads = false;
+ }
- void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
- {
- string run_from, run_to;
- clear_flags();
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+ {
+ string run_from, run_to;
+ clear_flags();
- size_t argidx;
- for (argidx = 1; argidx < args.size(); argidx++)
- {
- if (args[argidx] == "-family" && argidx+1 < args.size()) {
- family_opt = args[++argidx];
- continue;
- }
- if (args[argidx] == "-top" && argidx+1 < args.size()) {
- top_opt = "-top " + args[++argidx];
- continue;
- }
- if (args[argidx] == "-vqm" && argidx+1 < args.size()) {
- vout_file = args[++argidx];
- continue;
- }
- if (args[argidx] == "-vpr" && argidx+1 < args.size()) {
- blif_file = args[++argidx];
- continue;
- }
- if (args[argidx] == "-run" && argidx+1 < args.size()) {
- size_t pos = args[argidx+1].find(':');
- if (pos == std::string::npos)
- break;
- run_from = args[++argidx].substr(0, pos);
- run_to = args[argidx].substr(pos+1);
- continue;
- }
- if (args[argidx] == "-noiopads") {
- noiopads = true;
- continue;
- }
- if (args[argidx] == "-nobram") {
- nobram = true;
- continue;
- }
- if (args[argidx] == "-noflatten") {
- flatten = false;
- continue;
- }
- if (args[argidx] == "-retime") {
- retime = true;
- continue;
- }
- break;
- }
- extra_args(args, argidx, design);
+ size_t argidx;
+ for (argidx = 1; argidx < args.size(); argidx++) {
+ if (args[argidx] == "-family" && argidx + 1 < args.size()) {
+ family_opt = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-top" && argidx + 1 < args.size()) {
+ top_opt = "-top " + args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-vqm" && argidx + 1 < args.size()) {
+ vout_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-vpr" && argidx + 1 < args.size()) {
+ blif_file = args[++argidx];
+ continue;
+ }
+ if (args[argidx] == "-run" && argidx + 1 < args.size()) {
+ size_t pos = args[argidx + 1].find(':');
+ if (pos == std::string::npos)
+ break;
+ run_from = args[++argidx].substr(0, pos);
+ run_to = args[argidx].substr(pos + 1);
+ continue;
+ }
+ if (args[argidx] == "-noiopads") {
+ noiopads = true;
+ continue;
+ }
+ if (args[argidx] == "-nobram") {
+ nobram = true;
+ continue;
+ }
+ if (args[argidx] == "-noflatten") {
+ flatten = false;
+ continue;
+ }
+ if (args[argidx] == "-retime") {
+ retime = true;
+ continue;
+ }
+ break;
+ }
+ extra_args(args, argidx, design);
- if (!design->full_selection())
- log_cmd_error("This command only operates on fully selected designs!\n");
- if (family_opt != "max10" && family_opt !="a10gx" && family_opt != "cyclonev" && family_opt !="cycloneiv" && family_opt !="cycloneive" && family_opt != "cyclone10")
- log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str());
+ if (!design->full_selection())
+ log_cmd_error("This command only operates on fully selected designs!\n");
+ if (family_opt != "max10" && family_opt != "a10gx" && family_opt != "cyclonev" && family_opt != "cycloneiv" &&
+ family_opt != "cycloneive" && family_opt != "cyclone10")
+ log_cmd_error("Invalid or not family specified: '%s'\n", family_opt.c_str());
- log_header(design, "Executing SYNTH_INTEL pass.\n");
- log_push();
+ log_header(design, "Executing SYNTH_INTEL pass.\n");
+ log_push();
- run_script(design, run_from, run_to);
+ run_script(design, run_from, run_to);
- log_pop();
- }
+ log_pop();
+ }
- void script() YS_OVERRIDE
- {
- if (check_label("begin"))
- {
- if(check_label("family") && family_opt=="max10")
- run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
- else if(check_label("family") && family_opt=="a10gx")
- run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
- else if(check_label("family") && family_opt=="cyclonev")
- run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
- else if(check_label("family") && family_opt=="cyclone10")
- run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
- else if(check_label("family") && family_opt=="cycloneiv")
- run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
- else
- run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
- // Misc and common cells
- run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
- run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
- run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
- }
+ void script() YS_OVERRIDE
+ {
+ if (check_label("begin")) {
+ if (check_label("family") && family_opt == "max10")
+ run("read_verilog -sv -lib +/intel/max10/cells_sim.v");
+ else if (check_label("family") && family_opt == "a10gx")
+ run("read_verilog -sv -lib +/intel/a10gx/cells_sim.v");
+ else if (check_label("family") && family_opt == "cyclonev")
+ run("read_verilog -sv -lib +/intel/cyclonev/cells_sim.v");
+ else if (check_label("family") && family_opt == "cyclone10")
+ run("read_verilog -sv -lib +/intel/cyclone10/cells_sim.v");
+ else if (check_label("family") && family_opt == "cycloneiv")
+ run("read_verilog -sv -lib +/intel/cycloneiv/cells_sim.v");
+ else
+ run("read_verilog -sv -lib +/intel/cycloneive/cells_sim.v");
+ // Misc and common cells
+ run("read_verilog -sv -lib +/intel/common/m9k_bb.v");
+ run("read_verilog -sv -lib +/intel/common/altpll_bb.v");
+ run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+ }
- if (flatten && check_label("flatten", "(unless -noflatten)"))
- {
- run("proc");
- run("flatten");
- run("tribuf -logic");
- run("deminout");
- }
+ if (flatten && check_label("flatten", "(unless -noflatten)")) {
+ run("proc");
+ run("flatten");
+ run("tribuf -logic");
+ run("deminout");
+ }
- if (check_label("coarse"))
- {
- run("synth -run coarse");
- }
+ if (check_label("coarse")) {
+ run("synth -run coarse");
+ }
- if (!nobram && check_label("bram", "(skip if -nobram)"))
- {
- run("memory_bram -rules +/intel/common/brams.txt");
- run("techmap -map +/intel/common/brams_map.v");
- }
+ if (!nobram && check_label("bram", "(skip if -nobram)")) {
+ run("memory_bram -rules +/intel/common/brams.txt");
+ run("techmap -map +/intel/common/brams_map.v");
+ }
- if (check_label("fine"))
- {
- run("opt -fast -mux_undef -undriven -fine -full");
- run("memory_map");
- run("opt -undriven -fine");
- run("dffsr2dff");
- run("dff2dffe -direct-match $_DFF_*");
- run("opt -fine");
- run("techmap -map +/techmap.v");
- run("opt -full");
- run("clean -purge");
- run("setundef -undriven -zero");
- if (retime || help_mode)
- run("abc -markgroups -dff", "(only if -retime)");
- }
+ if (check_label("fine")) {
+ run("opt -fast -mux_undef -undriven -fine -full");
+ run("memory_map");
+ run("opt -undriven -fine");
+ run("dffsr2dff");
+ run("dff2dffe -direct-match $_DFF_*");
+ run("opt -fine");
+ run("techmap -map +/techmap.v");
+ run("opt -full");
+ run("clean -purge");
+ run("setundef -undriven -zero");
+ if (retime || help_mode)
+ run("abc -markgroups -dff", "(only if -retime)");
+ }
- if (check_label("map_luts"))
- {
- if(family_opt=="a10gx" || family_opt=="cyclonev")
- run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
- else
- run("abc -lut 4" + string(retime ? " -dff" : ""));
- run("clean");
- }
+ if (check_label("map_luts")) {
+ if (family_opt == "a10gx" || family_opt == "cyclonev")
+ run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
+ else
+ run("abc -lut 4" + string(retime ? " -dff" : ""));
+ run("clean");
+ }
- if (check_label("map_cells"))
- {
- if (!noiopads)
- run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
- if(family_opt=="max10")
- run("techmap -map +/intel/max10/cells_map.v");
- else if(family_opt=="a10gx")
- run("techmap -map +/intel/a10gx/cells_map.v");
- else if(family_opt=="cyclonev")
- run("techmap -map +/intel/cyclonev/cells_map.v");
- else if(family_opt=="cyclone10")
- run("techmap -map +/intel/cyclone10/cells_map.v");
- else if(family_opt=="cycloneiv")
- run("techmap -map +/intel/cycloneiv/cells_map.v");
- else
- run("techmap -map +/intel/cycloneive/cells_map.v");
- run("dffinit -highlow -ff dffeas q power_up");
- run("clean -purge");
- }
+ if (check_label("map_cells")) {
+ if (!noiopads)
+ run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
+ if (family_opt == "max10")
+ run("techmap -map +/intel/max10/cells_map.v");
+ else if (family_opt == "a10gx")
+ run("techmap -map +/intel/a10gx/cells_map.v");
+ else if (family_opt == "cyclonev")
+ run("techmap -map +/intel/cyclonev/cells_map.v");
+ else if (family_opt == "cyclone10")
+ run("techmap -map +/intel/cyclone10/cells_map.v");
+ else if (family_opt == "cycloneiv")
+ run("techmap -map +/intel/cycloneiv/cells_map.v");
+ else
+ run("techmap -map +/intel/cycloneive/cells_map.v");
+ run("dffinit -highlow -ff dffeas q power_up");
+ run("clean -purge");
+ }
- if (check_label("check"))
- {
- run("hierarchy -check");
- run("stat");
- run("check -noinit");
- }
+ if (check_label("check")) {
+ run("hierarchy -check");
+ run("stat");
+ run("check -noinit");
+ }
- if (check_label("vqm"))
- {
- if (!vout_file.empty() || help_mode)
- run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
- help_mode ? "<file-name>" : vout_file.c_str()));
- }
+ if (check_label("vqm")) {
+ if (!vout_file.empty() || help_mode)
+ run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
+ help_mode ? "<file-name>" : vout_file.c_str()));
+ }
- if (check_label("vpr"))
- {
- if (!blif_file.empty() || help_mode)
- {
- run(stringf("opt_clean -purge"));
- run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
- }
- }
- }
+ if (check_label("vpr")) {
+ if (!blif_file.empty() || help_mode) {
+ run(stringf("opt_clean -purge"));
+ run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
+ }
+ }
+ }
} SynthIntelPass;
PRIVATE_NAMESPACE_END
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 704ab21b1..40789ddbe 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -17,6 +17,16 @@
*
*/
+// Convert negative-polarity reset to positive-polarity
+(* techmap_celltype = "$_DFF_NN0_" *)
+module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_PN0_" *)
+module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_NN1_" *)
+module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+(* techmap_celltype = "$_DFF_PN1_" *)
+module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
+
module \$__SHREG_ (input C, input D, input E, output Q);
parameter DEPTH = 0;
parameter [DEPTH-1:0] INIT = 0;
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt
index e6635d0e2..91632bcee 100644
--- a/techlibs/xilinx/drams.txt
+++ b/techlibs/xilinx/drams.txt
@@ -26,11 +26,15 @@ bram $__XILINX_RAM128X1D
endbram
match $__XILINX_RAM64X1D
+ min bits 5
+ min wports 1
make_outreg
or_next_if_better
endmatch
match $__XILINX_RAM128X1D
+ min bits 9
+ min wports 1
make_outreg
endmatch
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
index c61fd7070..13beaa6ae 100644
--- a/techlibs/xilinx/ff_map.v
+++ b/techlibs/xilinx/ff_map.v
@@ -22,26 +22,21 @@
`ifndef _NO_FFS
-`ifndef _NO_POS_SR
module \$_DFF_N_ (input D, C, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
module \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
module \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
module \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
+module \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
module \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
+module \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
module \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
+module \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
+module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
-`endif
-
-module \$_DFF_NN0_ (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-module \$_DFF_PN0_ (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-
-module \$_DFF_NN1_ (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-module \$_DFF_PN1_ (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule
-`endif
`endif
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 5820d6d61..f966115cd 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -25,18 +25,9 @@
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
-bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
+struct SynthXilinxPass : public ScriptPass
{
- if (label == run_from)
- active = true;
- if (label == run_to)
- active = false;
- return active;
-}
-
-struct SynthXilinxPass : public Pass
-{
- SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
+ SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
void help() YS_OVERRIDE
{
@@ -51,6 +42,10 @@ struct SynthXilinxPass : public Pass
log(" -top <module>\n");
log(" use the specified module as top module\n");
log("\n");
+ log(" -arch {xcup|xcu|xc7|xc6s}\n");
+ log(" run synthesis for the specified Xilinx architecture\n");
+ log(" default: xc7\n");
+ log("\n");
log(" -edif <file>\n");
log(" write the design to the specified edif file. writing of an output file\n");
log(" is omitted if this parameter is not specified.\n");
@@ -63,6 +58,9 @@ struct SynthXilinxPass : public Pass
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
log(" (this feature is experimental and incomplete)\n");
log("\n");
+ log(" -nocarry\n");
+ log(" disable inference of carry chains\n");
+ log("\n");
log(" -nobram\n");
log(" disable inference of block rams\n");
log("\n");
@@ -72,6 +70,9 @@ struct SynthXilinxPass : public Pass
log(" -nosrl\n");
log(" disable inference of shift registers\n");
log("\n");
+ log(" -nomux\n");
+ log(" disable inference of wide multiplexers\n");
+ log("\n");
log(" -run <from_label>:<to_label>\n");
log(" only run the commands between the labels (see below). an empty\n");
log(" from label is synonymous to 'begin', and empty to label is\n");
@@ -88,80 +89,34 @@ struct SynthXilinxPass : public Pass
log("\n");
log("\n");
log("The following commands are executed by this synthesis command:\n");
- log("\n");
- log(" begin:\n");
- log(" read_verilog -lib +/xilinx/cells_sim.v\n");
- log(" read_verilog -lib +/xilinx/cells_xtra.v\n");
- log(" read_verilog -lib +/xilinx/brams_bb.v\n");
- log(" hierarchy -check -top <top>\n");
- log("\n");
- log(" flatten: (only if -flatten)\n");
- log(" proc\n");
- log(" flatten\n");
- log("\n");
- log(" coarse:\n");
- log(" synth -run coarse\n");
- log("\n");
- log(" bram: (only executed when '-nobram' is not given)\n");
- log(" memory_bram -rules +/xilinx/brams.txt\n");
- log(" techmap -map +/xilinx/brams_map.v\n");
- log("\n");
- log(" dram: (only executed when '-nodram' is not given)\n");
- log(" memory_bram -rules +/xilinx/drams.txt\n");
- log(" techmap -map +/xilinx/drams_map.v\n");
- log("\n");
- log(" fine:\n");
- log(" opt -fast\n");
- log(" memory_map\n");
- log(" dffsr2dff\n");
- log(" dff2dffe\n");
- log(" techmap -map +/xilinx/arith_map.v\n");
- log(" opt -fast\n");
- log("\n");
- log(" map_cells:\n");
- log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
- log(" pmux2shiftx (without '-nosrl' only)\n");
- log(" opt_expr -mux_undef (without '-nosrl' only)\n");
- log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
- log(" techmap -map +/xilinx/cells_map.v\n");
- log(" clean\n");
- log("\n");
- log(" map_luts:\n");
- log(" opt -full\n");
- log(" techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
- log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n");
- log(" clean\n");
- log(" shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
- log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
- log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n");
- log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
- log(" clean\n");
- log("\n");
- log(" check:\n");
- log(" hierarchy -check\n");
- log(" stat\n");
- log(" check -noinit\n");
- log("\n");
- log(" edif: (only if -edif)\n");
- log(" write_edif <file-name>\n");
- log("\n");
- log(" blif: (only if -blif)\n");
- log(" write_blif <file-name>\n");
+ help_script();
log("\n");
}
+
+ std::string top_opt, edif_file, blif_file, abc, arch;
+ bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
+
+ void clear_flags() YS_OVERRIDE
+ {
+ top_opt = "-auto-top";
+ edif_file.clear();
+ blif_file.clear();
+ abc = "abc";
+ flatten = false;
+ retime = false;
+ vpr = false;
+ nocarry = false;
+ nobram = false;
+ nodram = false;
+ nosrl = false;
+ nomux = false;
+ arch = "xc7";
+ }
+
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
- std::string top_opt = "-auto-top";
- std::string edif_file;
- std::string blif_file;
std::string run_from, run_to;
- std::string abc = "abc";
- bool flatten = false;
- bool retime = false;
- bool vpr = false;
- bool nobram = false;
- bool nodram = false;
- bool nosrl = false;
+ clear_flags();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
@@ -170,6 +125,10 @@ struct SynthXilinxPass : public Pass
top_opt = "-top " + args[++argidx];
continue;
}
+ if (args[argidx] == "-arch" && argidx+1 < args.size()) {
+ arch = args[++argidx];
+ continue;
+ }
if (args[argidx] == "-edif" && argidx+1 < args.size()) {
edif_file = args[++argidx];
continue;
@@ -198,6 +157,10 @@ struct SynthXilinxPass : public Pass
vpr = true;
continue;
}
+ if (args[argidx] == "-nocarry") {
+ nocarry = true;
+ continue;
+ }
if (args[argidx] == "-nobram") {
nobram = true;
continue;
@@ -209,7 +172,11 @@ struct SynthXilinxPass : public Pass
if (args[argidx] == "-nosrl") {
nosrl = true;
continue;
- }
+ }
+ if (args[argidx] == "-nomux") {
+ nomux = true;
+ continue;
+ }
if (args[argidx] == "-abc9") {
abc = "abc9";
continue;
@@ -218,131 +185,150 @@ struct SynthXilinxPass : public Pass
}
extra_args(args, argidx, design);
+ if (arch != "xcup" && arch != "xcu" && arch != "xc7" && arch != "xc6s")
+ log_cmd_error("Invalid Xilinx -arch setting: %s\n", arch.c_str());
+
if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n");
- bool active = run_from.empty();
-
log_header(design, "Executing SYNTH_XILINX pass.\n");
log_push();
- if (check_label(active, run_from, run_to, "begin"))
- {
- if (vpr) {
- Pass::call(design, "read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
- } else {
- Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
- }
+ run_script(design, run_from, run_to);
- Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
+ log_pop();
+ }
- if (!nobram) {
- Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
- }
+ void script() YS_OVERRIDE
+ {
+ if (check_label("begin")) {
+ if (vpr)
+ run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+ else
+ run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
- Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
- }
+ run("read_verilog -lib +/xilinx/cells_xtra.v");
- if (flatten && check_label(active, run_from, run_to, "flatten"))
- {
- Pass::call(design, "proc");
- Pass::call(design, "flatten");
- }
+ if (!nobram || help_mode)
+ run("read_verilog -lib +/xilinx/brams_bb.v", "(skip if '-nobram')");
- if (check_label(active, run_from, run_to, "coarse"))
- {
- Pass::call(design, "synth -run coarse");
+ run(stringf("hierarchy -check %s", top_opt.c_str()));
}
- if (check_label(active, run_from, run_to, "bram"))
- {
- if (!nobram) {
- Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
- Pass::call(design, "techmap -map +/xilinx/brams_map.v");
+ if (check_label("flatten", "(with '-flatten' only)")) {
+ if (flatten || help_mode) {
+ run("proc");
+ run("flatten");
}
}
- if (check_label(active, run_from, run_to, "dram"))
- {
- if (!nodram) {
- Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
- Pass::call(design, "techmap -map +/xilinx/drams_map.v");
- }
+ if (check_label("coarse")) {
+ run("synth -run coarse");
+
+ //if (!nomux || help_mode)
+ // run("muxpack", "(skip if '-nomux')");
+
+ // shregmap -tech xilinx can cope with $shiftx and $mux
+ // cells for identifying variable-length shift registers,
+ // so attempt to convert $pmux-es to the former
+ // Also: wide multiplexer inference benefits from this too
+ if (!(nosrl && nomux) || help_mode)
+ run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
+
+ // Run a number of peephole optimisations, including one
+ // that optimises $mul cells driving $shiftx's B input
+ // and that aids wide mux analysis
+ run("peepopt");
}
- if (check_label(active, run_from, run_to, "fine"))
- {
- Pass::call(design, "opt -fast");
- Pass::call(design, "memory_map");
- Pass::call(design, "dffsr2dff");
- Pass::call(design, "dff2dffe");
-
- if (vpr) {
- Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
- } else {
- Pass::call(design, "techmap -map +/xilinx/arith_map.v");
+ if (check_label("bram", "(skip if '-nobram')")) {
+ if (!nobram || help_mode) {
+ run("memory_bram -rules +/xilinx/brams.txt");
+ run("techmap -map +/xilinx/brams_map.v");
}
+ }
- Pass::call(design, "hierarchy -check");
- Pass::call(design, "opt -fast");
+ if (check_label("dram", "(skip if '-nodram')")) {
+ if (!nodram || help_mode) {
+ run("memory_bram -rules +/xilinx/drams.txt");
+ run("techmap -map +/xilinx/drams_map.v");
+ }
}
- if (check_label(active, run_from, run_to, "map_cells"))
- {
- if (!nosrl) {
+ if (check_label("fine")) {
+ run("opt -fast -full");
+ run("memory_map");
+ run("dffsr2dff");
+ run("dff2dffe");
+ run("opt -full");
+
+ if (!nosrl || help_mode) {
// shregmap operates on bit-level flops, not word-level,
// so break those down here
- Pass::call(design, "simplemap t:$dff t:$dffe");
- // shregmap -tech xilinx can cope with $shiftx and $mux
- // cells for identifiying variable-length shift registers,
- // so attempt to convert $pmux-es to the former
- Pass::call(design, "pmux2shiftx");
- // pmux2shiftx can leave behind a $pmux with a single entry
- // -- need this to clean that up before shregmap
- Pass::call(design, "opt_expr -mux_undef");
+ run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
// shregmap with '-tech xilinx' infers variable length shift regs
- Pass::call(design, "shregmap -tech xilinx -minlen 3");
+ run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
}
- Pass::call(design, "techmap -map +/xilinx/cells_map.v");
- Pass::call(design, "clean");
+ std::string techmap_files = " -map +/techmap.v";
+ if (help_mode)
+ techmap_files += " [-map +/xilinx/mux_map.v]";
+ else if (!nomux)
+ techmap_files += " -map +/xilinx/mux_map.v";
+ if (help_mode)
+ techmap_files += " [-map +/xilinx/arith_map.v]";
+ else if (!nocarry) {
+ techmap_files += " -map +/xilinx/arith_map.v";
+ if (vpr)
+ techmap_files += " -D _EXPLICIT_CARRY";
+ else if (abc == "abc9")
+ techmap_files += " -D _CLB_CARRY";
+ }
+ run("techmap " + techmap_files);
+ run("opt -fast");
}
- if (check_label(active, run_from, run_to, "map_luts"))
- {
- Pass::call(design, "opt -full");
- Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
- Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
- Pass::call(design, "clean");
+ if (check_label("map_cells")) {
+ if (!nomux || help_mode)
+ run("muxcover -mux8 -mux16", "(skip if '-nomux')");
+ run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
+ run("clean");
+ }
+
+ if (check_label("map_luts")) {
+ if (abc == "abc9")
+ run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : ""));
+ else if (help_mode)
+ run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
+ else
+ run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+ run("clean");
+
// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
- if (!nosrl)
- Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
- Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
- Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+ if (!nosrl || help_mode)
+ run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+ run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v");
+ run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
- Pass::call(design, "clean");
+ run("clean");
}
- if (check_label(active, run_from, run_to, "check"))
- {
- Pass::call(design, "hierarchy -check");
- Pass::call(design, "stat");
- Pass::call(design, "check -noinit");
+ if (check_label("check")) {
+ run("hierarchy -check");
+ run("stat -tech xilinx");
+ run("check -noinit");
}
- if (check_label(active, run_from, run_to, "edif"))
- {
- if (!edif_file.empty())
- Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str()));
- }
- if (check_label(active, run_from, run_to, "blif"))
- {
- if (!blif_file.empty())
- Pass::call(design, stringf("write_blif %s", edif_file.c_str()));
+ if (check_label("edif")) {
+ if (!edif_file.empty() || help_mode)
+ run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
}
- log_pop();
+ if (check_label("blif")) {
+ if (!blif_file.empty() || help_mode)
+ run(stringf("write_blif %s", edif_file.c_str()));
+ }
}
} SynthXilinxPass;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 03:34:03 +0000