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Diffstat (limited to 'tests/arch/xilinx/fsm.ys')
| -rw-r--r-- | tests/arch/xilinx/fsm.ys | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys new file mode 100644 index 000000000..2a72c34e8 --- /dev/null +++ b/tests/arch/xilinx/fsm.ys @@ -0,0 +1,18 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 5 t:FDRE +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT4 +select -assert-count 4 t:LUT6 +select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D |