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-rw-r--r--tests/xilinx/latches.ys13
1 files changed, 0 insertions, 13 deletions
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
deleted file mode 100644
index bd1dffd21..000000000
--- a/tests/xilinx/latches.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog latches.v
-
-proc
-flatten
-equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-
-design -load preopt
-synth_xilinx
-cd top
-select -assert-count 1 t:LUT1
-select -assert-count 2 t:LUT3
-select -assert-count 3 t:LDCE
-select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D