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-rw-r--r--tests/xilinx/.gitignore4
-rw-r--r--tests/xilinx/dsp_simd.ys25
-rw-r--r--tests/xilinx/latches.v58
-rw-r--r--tests/xilinx/latches.ys13
-rw-r--r--tests/xilinx/macc.sh3
-rw-r--r--tests/xilinx/macc.v84
-rw-r--r--tests/xilinx/macc.ys31
-rw-r--r--tests/xilinx/macc_tb.v96
-rw-r--r--tests/xilinx/mul_unsigned.v30
-rw-r--r--tests/xilinx/mul_unsigned.ys10
-rw-r--r--tests/xilinx/pmgen_xilinx_srl.ys57
-rwxr-xr-xtests/xilinx/run-test.sh20
-rw-r--r--tests/xilinx/xilinx_srl.v40
-rw-r--r--tests/xilinx/xilinx_srl.ys67
14 files changed, 0 insertions, 538 deletions
diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
deleted file mode 100644
index 54733fb71..000000000
--- a/tests/xilinx/.gitignore
+++ /dev/null
@@ -1,4 +0,0 @@
-/*.log
-/*.out
-/run-test.mk
-/*_uut.v
diff --git a/tests/xilinx/dsp_simd.ys b/tests/xilinx/dsp_simd.ys
deleted file mode 100644
index 956952327..000000000
--- a/tests/xilinx/dsp_simd.ys
+++ /dev/null
@@ -1,25 +0,0 @@
-read_verilog <<EOT
-module simd(input [12*4-1:0] a, input [12*4-1:0] b, (* use_dsp="simd" *) output [7*12-1:0] o12, (* use_dsp="simd" *) output [2*24-1:0] o24);
-generate
- genvar i;
- // 4 x 12-bit adder
- for (i = 0; i < 4; i++)
- assign o12[i*12+:12] = a[i*12+:12] + b[i*12+:12];
- // 2 x 24-bit subtract
- for (i = 0; i < 2; i++)
- assign o24[i*24+:24] = a[i*24+:24] - b[i*24+:24];
-endgenerate
-reg [3*12-1:0] ro;
-always @* begin
- ro[0*12+:12] = a[0*10+:10] + b[0*10+:10];
- ro[1*12+:12] = a[1*10+:10] + b[1*10+:10];
- ro[2*12+:12] = a[2*8+:8] + b[2*8+:8];
-end
-assign o12[4*12+:3*12] = ro;
-endmodule
-EOT
-
-proc
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
-design -load postopt
-select -assert-count 3 t:DSP48E1
diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
deleted file mode 100644
index 83bad7f35..000000000
--- a/tests/xilinx/latches.v
+++ /dev/null
@@ -1,58 +0,0 @@
-module latchp
- ( input d, en, output reg q );
- always @*
- if ( en )
- q <= d;
-endmodule
-
-module latchn
- ( input d, en, output reg q );
- always @*
- if ( !en )
- q <= d;
-endmodule
-
-module latchsr
- ( input d, en, clr, pre, output reg q );
- always @*
- if ( clr )
- q <= 1'b0;
- else if ( pre )
- q <= 1'b1;
- else if ( en )
- q <= d;
-endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
- .en (clk ),
- .d (a ),
- .q (b )
- );
-
-
-latchn u_latchn (
- .en (clk ),
- .d (a ),
- .q (b1 )
- );
-
-
-latchsr u_latchsr (
- .en (clk ),
- .clr (clr),
- .pre (pre),
- .d (a ),
- .q (b2 )
- );
-
-endmodule
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
deleted file mode 100644
index bd1dffd21..000000000
--- a/tests/xilinx/latches.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog latches.v
-
-proc
-flatten
-equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-
-design -load preopt
-synth_xilinx
-cd top
-select -assert-count 1 t:LUT1
-select -assert-count 2 t:LUT3
-select -assert-count 3 t:LDCE
-select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D
diff --git a/tests/xilinx/macc.sh b/tests/xilinx/macc.sh
deleted file mode 100644
index 86e4c2bb6..000000000
--- a/tests/xilinx/macc.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v
-iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../techlibs/xilinx/cells_sim.v
-vvp -N ./test_macc
diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
deleted file mode 100644
index e36b2bab1..000000000
--- a/tests/xilinx/macc.v
+++ /dev/null
@@ -1,84 +0,0 @@
-// Signed 40-bit streaming accumulator with 16-bit inputs
-// File: HDL_Coding_Techniques/multipliers/multipliers4.v
-//
-// Source:
-// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
-//
-module macc # (parameter SIZEIN = 16, SIZEOUT = 40) (
- input clk, ce, sload,
- input signed [SIZEIN-1:0] a, b,
- output signed [SIZEOUT-1:0] accum_out
-);
-// Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg;
-reg sload_reg;
-reg signed [2*SIZEIN-1:0] mult_reg;
-reg signed [SIZEOUT-1:0] adder_out, old_result;
-always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
- if (sload_reg)
- old_result <= 0;
- else
- // 'sload' is now active (=low) and opens the accumulation loop.
- // The accumulator takes the next multiplier output in
- // the same cycle.
- old_result <= adder_out;
-end
-
-always @(posedge clk)
- if (ce)
- begin
- a_reg <= a;
- b_reg <= b;
- mult_reg <= a_reg * b_reg;
- sload_reg <= sload;
- // Store accumulation result into a register
- adder_out <= old_result + mult_reg;
- end
-
-// Output accumulation result
-assign accum_out = adder_out;
-
-endmodule
-
-// Adapted variant of above
-module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
- input clk,
- input ce,
- input rst,
- input signed [SIZEIN-1:0] a, b,
- output signed [SIZEOUT-1:0] accum_out,
- output overflow
-);
-// Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2;
-reg signed [2*SIZEIN-1:0] mult_reg = 0;
-reg signed [SIZEOUT:0] adder_out = 0;
-reg overflow_reg;
-always @(posedge clk) begin
- //if (ce)
- begin
- a_reg <= a;
- b_reg <= b;
- a_reg2 <= a_reg;
- b_reg2 <= b_reg;
- mult_reg <= a_reg2 * b_reg2;
- // Store accumulation result into a register
- adder_out <= adder_out + mult_reg;
- overflow_reg <= overflow;
- end
- if (rst) begin
- a_reg <= 0;
- a_reg2 <= 0;
- b_reg <= 0;
- b_reg2 <= 0;
- mult_reg <= 0;
- adder_out <= 0;
- overflow_reg <= 1'b0;
- end
-end
-assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg;
-
-// Output accumulation result
-assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;
-
-endmodule
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
deleted file mode 100644
index 417a3b21b..000000000
--- a/tests/xilinx/macc.ys
+++ /dev/null
@@ -1,31 +0,0 @@
-read_verilog macc.v
-design -save read
-
-proc
-hierarchy -top macc
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd macc # Constrain all select calls below inside the top module
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:FDRE
-select -assert-count 1 t:DSP48E1
-select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
-
-design -load read
-proc
-hierarchy -top macc2
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd macc2 # Constrain all select calls below inside the top module
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:DSP48E1
-select -assert-count 1 t:FDRE
-select -assert-count 1 t:LUT2
-select -assert-count 41 t:LUT3
-select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D
diff --git a/tests/xilinx/macc_tb.v b/tests/xilinx/macc_tb.v
deleted file mode 100644
index 64aed05c4..000000000
--- a/tests/xilinx/macc_tb.v
+++ /dev/null
@@ -1,96 +0,0 @@
-`timescale 1ns / 1ps
-
-module testbench;
-
- parameter SIZEIN = 16, SIZEOUT = 40;
- reg clk, ce, rst;
- reg signed [SIZEIN-1:0] a, b;
- output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
- output REF_overflow, overflow;
-
- integer errcount = 0;
-
- reg ERROR_FLAG = 0;
-
- task clkcycle;
- begin
- #5;
- clk = ~clk;
- #10;
- clk = ~clk;
- #2;
- ERROR_FLAG = 0;
- if (REF_accum_out !== accum_out) begin
- $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out);
- errcount = errcount + 1;
- ERROR_FLAG = 1;
- end
- if (REF_overflow !== overflow) begin
- $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow);
- errcount = errcount + 1;
- ERROR_FLAG = 1;
- end
- #3;
- end
- endtask
-
- initial begin
- //$dumpfile("test_macc.vcd");
- //$dumpvars(0, testbench);
-
- #2;
- clk = 1'b0;
- ce = 1'b0;
- a = 0;
- b = 0;
-
- rst = 1'b1;
- repeat (10) begin
- #10;
- clk = 1'b1;
- #10;
- clk = 1'b0;
- #10;
- clk = 1'b1;
- #10;
- clk = 1'b0;
- end
- rst = 1'b0;
-
- repeat (10000) begin
- clkcycle;
- ce = 1; //$urandom & $urandom;
- //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
- a = $urandom & ~(1 << (SIZEIN-1));
- b = $urandom & ~(1 << (SIZEIN-1));
- end
-
- if (errcount == 0) begin
- $display("All tests passed.");
- $finish;
- end else begin
- $display("Caught %1d errors.", errcount);
- $stop;
- end
- end
-
- macc2 ref (
- .clk(clk),
- .ce(ce),
- .rst(rst),
- .a(a),
- .b(b),
- .accum_out(REF_accum_out),
- .overflow(REF_overflow)
- );
-
- macc2_uut uut (
- .clk(clk),
- .ce(ce),
- .rst(rst),
- .a(a),
- .b(b),
- .accum_out(accum_out),
- .overflow(overflow)
- );
-endmodule
diff --git a/tests/xilinx/mul_unsigned.v b/tests/xilinx/mul_unsigned.v
deleted file mode 100644
index e3713a642..000000000
--- a/tests/xilinx/mul_unsigned.v
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
-Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89].
-*/
-
-// Unsigned 16x24-bit Multiplier
-// 1 latency stage on operands
-// 3 latency stage after the multiplication
-// File: multipliers2.v
-//
-module mul_unsigned (clk, A, B, RES);
-parameter WIDTHA = /*16*/ 6;
-parameter WIDTHB = /*24*/ 9;
-input clk;
-input [WIDTHA-1:0] A;
-input [WIDTHB-1:0] B;
-output [WIDTHA+WIDTHB-1:0] RES;
-reg [WIDTHA-1:0] rA;
-reg [WIDTHB-1:0] rB;
-reg [WIDTHA+WIDTHB-1:0] M [3:0];
-integer i;
-always @(posedge clk)
- begin
- rA <= A;
- rB <= B;
- M[0] <= rA * rB;
- for (i = 0; i < 3; i = i+1)
- M[i+1] <= M[i];
- end
-assign RES = M[3];
-endmodule
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
deleted file mode 100644
index 77990bd68..000000000
--- a/tests/xilinx/mul_unsigned.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog mul_unsigned.v
-proc
-hierarchy -top mul_unsigned
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mul_unsigned # Constrain all select calls below inside the top module
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:DSP48E1
-select -assert-count 30 t:FDRE
-select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D
diff --git a/tests/xilinx/pmgen_xilinx_srl.ys b/tests/xilinx/pmgen_xilinx_srl.ys
deleted file mode 100644
index ea2f20487..000000000
--- a/tests/xilinx/pmgen_xilinx_srl.ys
+++ /dev/null
@@ -1,57 +0,0 @@
-read_verilog -icells <<EOT
-module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, output SO);
- parameter DEPTH = 1;
- parameter [DEPTH-1:0] INIT = 0;
- parameter CLKPOL = 1;
- parameter ENPOL = 2;
-
- wire pos_clk = C == CLKPOL;
- reg pos_en;
- always @(E)
- if (ENPOL == 2) pos_en = 1'b1;
- else pos_en = (E == ENPOL[0]);
-
- reg [DEPTH-1:0] r;
- always @(posedge pos_clk)
- if (pos_en)
- r <= {r[DEPTH-2:0], D};
-
- assign Q = r[L];
- assign SO = r[DEPTH-1];
-endmodule
-EOT
-read_verilog +/xilinx/cells_sim.v
-proc
-design -save model
-
-test_pmgen -generate xilinx_srl.fixed
-hierarchy -top pmtest_xilinx_srl_pm_fixed
-flatten; opt_clean
-
-design -save gold
-xilinx_srl -fixed
-techmap -autoproc -map %model
-design -stash gate
-
-design -copy-from gold -as gold pmtest_xilinx_srl_pm_fixed
-design -copy-from gate -as gate pmtest_xilinx_srl_pm_fixed
-dff2dffe -unmap # sat does not support flops-with-enable yet
-miter -equiv -flatten -make_assert gold gate miter
-sat -set-init-zero -seq 5 -verify -prove-asserts miter
-
-design -load model
-
-test_pmgen -generate xilinx_srl.variable
-hierarchy -top pmtest_xilinx_srl_pm_variable
-flatten; opt_clean
-
-design -save gold
-xilinx_srl -variable
-techmap -autoproc -map %model
-design -stash gate
-
-design -copy-from gold -as gold pmtest_xilinx_srl_pm_variable
-design -copy-from gate -as gate pmtest_xilinx_srl_pm_variable
-dff2dffe -unmap # sat does not support flops-with-enable yet
-miter -equiv -flatten -make_assert gold gate miter
-sat -set-init-zero -seq 5 -verify -prove-asserts miter
diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh
deleted file mode 100755
index ea56b70f0..000000000
--- a/tests/xilinx/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
- echo "all:: run-$x"
- echo "run-$x:"
- echo " @echo 'Running $x..'"
- echo " @../../yosys -ql ${x%.ys}.log $x"
-done
-for s in *.sh; do
- if [ "$s" != "run-test.sh" ]; then
- echo "all:: run-$s"
- echo "run-$s:"
- echo " @echo 'Running $s..'"
- echo " @bash $s"
- fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/xilinx/xilinx_srl.v b/tests/xilinx/xilinx_srl.v
deleted file mode 100644
index bc2a15ab2..000000000
--- a/tests/xilinx/xilinx_srl.v
+++ /dev/null
@@ -1,40 +0,0 @@
-module xilinx_srl_static_test(input i, clk, output [1:0] q);
-reg head = 1'b0;
-reg [3:0] shift1 = 4'b0000;
-reg [3:0] shift2 = 4'b0000;
-
-always @(posedge clk) begin
- head <= i;
- shift1 <= {shift1[2:0], head};
- shift2 <= {shift2[2:0], head};
-end
-
-assign q = {shift2[3], shift1[3]};
-endmodule
-
-module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q);
-reg head = 1'b0;
-reg [3:0] shift1 = 4'b0000;
-reg [3:0] shift2 = 4'b0000;
-
-always @(posedge clk) begin
- head <= i;
- shift1 <= {shift1[2:0], head};
- shift2 <= {shift2[2:0], head};
-end
-
-assign q = {shift2[l2], shift1[l1]};
-endmodule
-
-module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q);
-parameter CLKPOL = 1;
-parameter ENPOL = 1;
-parameter DEPTH = 1;
-parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}};
-reg [DEPTH-1:0] r = INIT;
-wire clk = C ^ CLKPOL;
-always @(posedge C)
- if (E)
- r <= { r[DEPTH-2:0], D };
-assign Q = r[L];
-endmodule
diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys
deleted file mode 100644
index b8df0e55a..000000000
--- a/tests/xilinx/xilinx_srl.ys
+++ /dev/null
@@ -1,67 +0,0 @@
-read_verilog xilinx_srl.v
-design -save read
-
-design -copy-to model $__XILINX_SHREG_
-hierarchy -top xilinx_srl_static_test
-prep
-design -save gold
-
-techmap
-xilinx_srl -fixed
-opt
-
-# stat
-# show -width
-select -assert-count 1 t:$_DFF_P_
-select -assert-count 2 t:$__XILINX_SHREG_
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
-prep
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-dump gate
-sat -verify -prove-asserts -show-ports -seq 5 miter
-
-#design -load gold
-#stat
-
-#design -load gate
-#stat
-
-##########
-
-design -load read
-design -copy-to model $__XILINX_SHREG_
-hierarchy -top xilinx_srl_variable_test
-prep
-design -save gold
-
-xilinx_srl -variable
-opt
-
-#stat
-# show -width
-# write_verilog -noexpr -norename
-select -assert-count 1 t:$dff
-select -assert-count 1 t:$dff r:WIDTH=1 %i
-select -assert-count 2 t:$__XILINX_SHREG_
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_
-prep
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports -seq 5 miter
-
-# design -load gold
-# stat
-
-# design -load gate
-# stat
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 20:31:21 +0000