diff options
Diffstat (limited to 'tests')
241 files changed, 3285 insertions, 1374 deletions
diff --git a/tests/asicworld/run-test.sh b/tests/asicworld/run-test.sh index bf27d15f8..24983f1a5 100755 --- a/tests/asicworld/run-test.sh +++ b/tests/asicworld/run-test.sh @@ -1,3 +1,2 @@ #!/bin/bash -make -C ../.. || exit 1 -exec bash ../tools/autotest.sh *.v +exec ${MAKE:-make} -f ../tools/autotest.mk EXTRA_FLAGS="-e" *.v diff --git a/tests/fsm/.gitignore b/tests/fsm/.gitignore new file mode 100644 index 000000000..9c595a6fb --- /dev/null +++ b/tests/fsm/.gitignore @@ -0,0 +1 @@ +temp diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py new file mode 100644 index 000000000..b5b4626df --- /dev/null +++ b/tests/fsm/generate.py @@ -0,0 +1,109 @@ +#!/usr/bin/python + +from __future__ import division +from __future__ import print_function + +import sys +import random +from contextlib import contextmanager + +# set to 'True' to compare verific with yosys +test_verific = False + +@contextmanager +def redirect_stdout(new_target): + old_target, sys.stdout = sys.stdout, new_target + try: + yield new_target + finally: + sys.stdout = old_target + +def random_expr(variables): + c = random.choice(['bin', 'uni', 'var', 'const']) + if c == 'bin': + op = random.choice(['+', '-', '*', '<', '<=', '==', '!=', '>=', '>', '<<', '>>', '<<<', '>>>', '|', '&', '^', '~^', '||', '&&']) + return "(%s %s %s)" % (random_expr(variables), op, random_expr(variables)) + if c == 'uni': + op = random.choice(['+', '-', '~', '|', '&', '^', '~^', '!', '$signed', '$unsigned']) + return "%s(%s)" % (op, random_expr(variables)) + if c == 'var': + return random.choice(variables) + if c == 'const': + bits = random.randint(1, 32) + return "%d'd%s" % (bits, random.randint(0, 2**bits-1)) + raise AssertionError + +for idx in range(50): + with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): + rst2 = random.choice([False, True]) + if rst2: + print('module uut_%05d(clk, rst1, rst2, rst, a, b, c, x, y, z);' % (idx)) + print(' input clk, rst1, rst2;') + print(' output rst;') + print(' assign rst = rst1 || rst2;') + else: + print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx)) + print(' input clk, rst;') + variables=['a', 'b', 'c', 'x', 'y', 'z'] + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] y;' % (random.choice(['', ' signed']), random.randint(0, 31))) + print(' output reg%s [%d:0] z;' % (random.choice(['', ' signed']), random.randint(0, 31))) + state_bits = random.randint(5, 16); + print(' %sreg [%d:0] state;' % (random.choice(['', '(* fsm_encoding = "one-hot" *)', + '(* fsm_encoding = "binary" *)']), state_bits-1)) + states=[] + for i in range(random.randint(2, 10)): + n = random.randint(0, 2**state_bits-1) + if n not in states: + states.append(n) + print(' always @(posedge clk) begin') + print(' if (%s) begin' % ('rst1' if rst2 else 'rst')) + print(' x <= %d;' % random.randint(0, 2**31-1)) + print(' y <= %d;' % random.randint(0, 2**31-1)) + print(' z <= %d;' % random.randint(0, 2**31-1)) + print(' state <= %d;' % random.choice(states)) + print(' end else begin') + print(' case (state)') + for state in states: + print(' %d: begin' % state) + for var in ('x', 'y', 'z'): + print(' %s <= %s;' % (var, random_expr(variables))) + next_states = states[:] + for i in range(random.randint(0, len(states))): + next_state = random.choice(next_states) + next_states.remove(next_state) + print(' if ((%s) %s (%s)) state <= %s;' % (random_expr(variables), + random.choice(['<', '<=', '>=', '>']), random_expr(variables), next_state)) + print(' end') + print(' endcase') + if rst2: + print(' if (rst2) begin') + print(' x <= a;') + print(' y <= b;') + print(' z <= c;') + print(' state <= %d;' % random.choice(states)) + print(' end') + print(' end') + print(' end') + print('endmodule') + with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): + if test_verific: + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;; rename uut_%05d gold' % idx) + print('verific -vlog2k temp/uut_%05d.v' % idx) + print('verific -import uut_%05d' % idx) + print('rename uut_%05d gate' % idx) + else: + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('cd gate') + print('opt; wreduce; share%s; opt; fsm;;' % random.choice(['', ' -aggressive'])) + print('cd ..') + print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') + print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in')) + diff --git a/tests/fsm/run-test.sh b/tests/fsm/run-test.sh new file mode 100755 index 000000000..57c2a5b12 --- /dev/null +++ b/tests/fsm/run-test.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +# run this test many times: +# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' + +set -e + +rm -rf temp +mkdir -p temp +echo "generating tests.." +python generate.py + +{ + all_targets="all_targets:" + echo "all: all_targets" + echo " @echo" + for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do + idx=$( printf "%05d" $i ) + echo "temp/uut_${idx}.log: temp/uut_${idx}.ys temp/uut_${idx}.v" + echo " @echo -n '[$i]'" + echo " @../../yosys -ql temp/uut_${idx}.out temp/uut_${idx}.ys" + echo " @mv temp/uut_${idx}.out temp/uut_${idx}.log" + echo " @grep -q 'SAT proof finished' temp/uut_${idx}.log && echo -n K || echo -n T" + all_targets="$all_targets temp/uut_${idx}.log" + done + echo "$all_targets" +} > temp/makefile + +echo "running tests.." +${MAKE:-make} -f temp/makefile + +exit 0 diff --git a/tests/hana/README b/tests/hana/README index 37049405d..b2a08fd47 100644 --- a/tests/hana/README +++ b/tests/hana/README @@ -2,13 +2,3 @@ This test cases are copied from the hana project: https://sourceforge.net/projects/sim-sim/ -** Copy tests from hana: ** -while read fn; do cp -v $fn ALL_TESTS/${fn//\//_}; done < <(find test -name '*.v' ! -name '*_gold.v') - -** Eliminate test's we can't parse atm: ** -rm -f test_synthesizability*.v -rm -f test_parse2synthtrans_latch_1_test.v -rm -f test_parse2synthtrans_always_1_test.v -rm -f test_parse2synthtrans_always_2_test.v -for x in test_*.v; do ../../yosys -b "" $x || rm $x; done - diff --git a/tests/hana/run-test.sh b/tests/hana/run-test.sh index b8e7231c7..fb766eec9 100755 --- a/tests/hana/run-test.sh +++ b/tests/hana/run-test.sh @@ -1,3 +1,2 @@ #!/bin/bash -make -C ../.. || exit 1 -exec bash ../tools/autotest.sh -l hana_vlib.v test_*.v +exec ${MAKE:-make} -f ../tools/autotest.mk EXTRA_FLAGS="-l hana_vlib.v -n 300 -e" test_*.v diff --git a/tests/hana/test_intermout.v b/tests/hana/test_intermout.v new file mode 100644 index 000000000..88b91ee4d --- /dev/null +++ b/tests/hana/test_intermout.v @@ -0,0 +1,418 @@ + +// test_intermout_always_comb_1_test.v +module f1_test(a, b, c, d, z); +input a, b, c, d; +output z; +reg z, temp1, temp2; + +always @(a or b or c or d) +begin + temp1 = a ^ b; + temp2 = c ^ d; + z = temp1 ^ temp2; +end + +endmodule + +// test_intermout_always_comb_3_test.v +module f2_test (in1, in2, out); +input in1, in2; +output reg out; + +always @ ( in1 or in2) + if(in1 > in2) + out = in1; + else + out = in2; +endmodule + +// test_intermout_always_comb_4_test.v +module f3_test(a, b, c); +input b, c; +output reg a; + +always @(b or c) begin +a = b; +a = c; +end +endmodule + +// test_intermout_always_comb_5_test.v +module f4_test(ctrl, in1, in2, out); +input ctrl; +input in1, in2; +output reg out; + +always @ (ctrl or in1 or in2) + if(ctrl) + out = in1 & in2; + else + out = in1 | in2; +endmodule + +// test_intermout_always_ff_3_test.v +module f5_NonBlockingEx(clk, merge, er, xmit, fddi, claim); +input clk, merge, er, xmit, fddi; +output reg claim; +reg fcr; + +always @(posedge clk) +begin + fcr = er | xmit; + + if(merge) + claim = fcr & fddi; + else + claim = fddi; +end +endmodule + +// test_intermout_always_ff_4_test.v +module f6_FlipFlop(clk, cs, ns); +input clk; +input [31:0] cs; +output [31:0] ns; +integer is; + +always @(posedge clk) + is <= cs; + +assign ns = is; +endmodule + +// test_intermout_always_ff_5_test.v +module f7_FlipFlop(clock, cs, ns); +input clock; +input [3:0] cs; +output reg [3:0] ns; +reg [3:0] temp; + +always @(posedge clock) +begin + temp = cs; + ns = temp; +end + +endmodule + +// test_intermout_always_ff_6_test.v +module f8_inc(clock, counter); + +input clock; +output reg [3:0] counter; +always @(posedge clock) + counter <= counter + 1; +endmodule + +// test_intermout_always_ff_8_test.v +module f9_NegEdgeClock(q, d, clk, reset); +input d, clk, reset; +output reg q; + +always @(negedge clk or negedge reset) + if(!reset) + q <= 1'b0; + else + q <= d; + +endmodule + +// test_intermout_always_ff_9_test.v +module f10_MyCounter (clock, preset, updown, presetdata, counter); +input clock, preset, updown; +input [1: 0] presetdata; +output reg [1:0] counter; + +always @(posedge clock) + if(preset) + counter <= presetdata; + else + if(updown) + counter <= counter + 1; + else + counter <= counter - 1; +endmodule + +// test_intermout_always_latch_1_test.v +module f11_test(en, in, out); +input en; +input [1:0] in; +output reg [2:0] out; + +always @ (en or in) + if(en) + out = in + 1; +endmodule + +// test_intermout_bufrm_1_test.v +module f12_test(input in, output out); +//no buffer removal +assign out = in; +endmodule + +// test_intermout_bufrm_2_test.v +module f13_test(input in, output out); +//intermediate buffers should be removed +wire w1, w2; +assign w1 = in; +assign w2 = w1; +assign out = w2; +endmodule + +// test_intermout_bufrm_6_test.v +module f14_test(in, out); +input in; +output out; + +wire w1, w2, w3, w4; +assign w1 = in; +assign w2 = w1; +assign w4 = w3; +assign out = w4; +f14_mybuf _f14_mybuf(w2, w3); +endmodule + +module f14_mybuf(in, out); +input in; +output out; +wire w1, w2, w3, w4; + +assign w1 = in; +assign w2 = w1; +assign out = w2; +endmodule + + +// test_intermout_bufrm_7_test.v +module f15_test(in1, in2, out); +input in1, in2; +output out; +// Y with cluster of f15_mybuf instances at the junction + +wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10; +assign w1 = in1; +assign w2 = w1; +assign w5 = in2; +assign w6 = w5; +assign w10 = w9; +assign out = w10; + +f15_mybuf _f15_mybuf0(w2, w3); +f15_mybuf _f15_mybuf1(w3, w4); + +f15_mybuf _f15_mybuf2(w6, w7); +f15_mybuf _f15_mybuf3(w7, w4); + +f15_mybuf _f15_mybuf4(w4, w8); +f15_mybuf _f15_mybuf5(w8, w9); +endmodule + +module f15_mybuf(in, out); +input in; +output out; +wire w1, w2, w3, w4; + +assign w1 = in; +assign w2 = w1; +assign out = w2; +endmodule + + +// test_intermout_exprs_add_test.v +module f16_test(out, in1, in2, vin1, vin2, vout1); +output out; +input in1, in2; +input [1:0] vin1; +input [2:0] vin2; +output [3:0] vout1; + +assign out = in1 + in2; +assign vout1 = vin1 + vin2; +endmodule + +// test_intermout_exprs_binlogic_test.v +module f17_test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 ); +input in1, in2; +input [1:0] vin1; +input [3:0] vin2; +input [1:0] vin3; +input [3:0] vin4; +output vout, vout1; +output out; + +assign out = in1 && in2; +assign vout = vin1 && vin2; +assign vout1 = vin3 || vin4; +endmodule + +// test_intermout_exprs_bitwiseneg_test.v +module f18_test(output out, input in, output [1:0] vout, input [1:0] vin); + +assign out = ~in; +assign vout = ~vin; +endmodule + +// test_intermout_exprs_buffer_test.v +module f19_buffer(in, out, vin, vout); +input in; +output out; +input [1:0] vin; +output [1:0] vout; + +assign out = in; +assign vout = vin; +endmodule + +// test_intermout_exprs_condexpr_mux_test.v +module f20_test(in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2); +input in1, in2, en1, ven1; +input [1:0] ven2; +output out; +input [1:0] vin1, vin2, vin3, vin4; +output [1:0] vout1, vout2; + +assign out = en1 ? in1 : in2; +assign vout1 = ven1 ? vin1 : vin2; +assign vout2 = ven2 ? vin3 : vin4; +endmodule + +// test_intermout_exprs_condexpr_tribuf_test.v +module f21_test(in, out, en, vin1, vout1, en1); +input in, en, en1; +output out; +input [1:0] vin1; +output [1:0] vout1; + +assign out = en ? in : 1'bz; +assign vout1 = en1 ? vin1 : 2'bzz; +endmodule + +// test_intermout_exprs_constshift_test.v +module f22_test(in, out, vin, vout, vin1, vout1, vin2, vout2); + +input in; +input [3:0] vin, vin1, vin2; +output [3:0] vout, vout1, vout2; +output out; + +assign out = in << 1; +assign vout = vin << 2; +assign vout1 = vin1 >> 2; +assign vout2 = vin2 >>> 2; +endmodule + +// test_intermout_exprs_const_test.v +module f23_test (out, vout); +output out; +output [7:0] vout; + +assign out = 1'b1; +assign vout = 9; +endmodule + +// test_intermout_exprs_div_test.v +module f24_test(out, in1, in2, vin1, vin2, vout1); +output out; +input in1, in2; +input [1:0] vin1; +input [2:0] vin2; +output [3:0] vout1; + +assign out = in1 / in2; +assign vout1 = vin1 / vin2; +endmodule + +// test_intermout_exprs_logicneg_test.v +module f25_test(out, vout, in, vin); +output out, vout; +input in; +input [3:0] vin; +assign out = !in; +assign vout = !vin; +endmodule + +// test_intermout_exprs_mod_test.v +module f26_test(out, in1, in2, vin1, vin2, vout1); +output out; +input in1, in2; +input [1:0] vin1; +input [2:0] vin2; +output [3:0] vout1; + +assign out = in1 % in2; +assign vout1 = vin1 % vin2; +endmodule + +// test_intermout_exprs_mul_test.v +module f27_test(out, in1, in2, vin1, vin2, vout1); +output out; +input in1, in2; +input [1:0] vin1; +input [2:0] vin2; +output [3:0] vout1; + +assign out = in1 * in2; +assign vout1 = vin1 * vin2; +endmodule + +// test_intermout_exprs_redand_test.v +module f28_test(output out, input [1:0] vin, output out1, input [3:0] vin1); + +assign out = &vin; +assign out1 = &vin1; +endmodule + +// test_intermout_exprs_redop_test.v +module f29_Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6); +input [1:0] A1; +input [1:0] A2; +input [1:0] A3; +input [1:0] A4; +input [1:0] A5; +input [1:0] A6; +output Y1, Y2, Y3, Y4, Y5, Y6; +//reg Y1, Y2, Y3, Y4, Y5, Y6; +assign Y1=&A1; //reduction AND +assign Y2=|A2; //reduction OR +assign Y3=~&A3; //reduction NAND +assign Y4=~|A4; //reduction NOR +assign Y5=^A5; //reduction XOR +assign Y6=~^A6; //reduction XNOR +endmodule + +// test_intermout_exprs_sub_test.v +module f30_test(out, in1, in2, vin1, vin2, vout1); +output out; +input in1, in2; +input [1:0] vin1; +input [2:0] vin2; +output [3:0] vout1; + +assign out = in1 - in2; +assign vout1 = vin1 - vin2; +endmodule + +// test_intermout_exprs_unaryminus_test.v +module f31_test(output out, input in, output [31:0] vout, input [31:0] vin); + +assign out = -in; +assign vout = -vin; +endmodule + +// test_intermout_exprs_unaryplus_test.v +module f32_test(output out, input in); + +assign out = +in; +endmodule + +// test_intermout_exprs_varshift_test.v +module f33_test(vin0, vout0); +input [2:0] vin0; +output reg [7:0] vout0; + +wire [7:0] myreg0, myreg1, myreg2; +integer i; +assign myreg0 = vout0 << vin0; + +assign myreg1 = myreg2 >> i; +endmodule diff --git a/tests/hana/test_intermout_always_comb_1_test.v b/tests/hana/test_intermout_always_comb_1_test.v deleted file mode 100644 index 2d5abc4a6..000000000 --- a/tests/hana/test_intermout_always_comb_1_test.v +++ /dev/null @@ -1,13 +0,0 @@ -module test(a, b, c, d, z); -input a, b, c, d; -output z; -reg z, temp1, temp2; - -always @(a or b or c or d) -begin - temp1 = a ^ b; - temp2 = c ^ d; - z = temp1 ^ temp2; -end - -endmodule diff --git a/tests/hana/test_intermout_always_comb_3_test.v b/tests/hana/test_intermout_always_comb_3_test.v deleted file mode 100644 index 234407efd..000000000 --- a/tests/hana/test_intermout_always_comb_3_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test (in1, in2, out); -input in1, in2; -output reg out; - -always @ ( in1 or in2) - if(in1 > in2) - out = in1; - else - out = in2; -endmodule diff --git a/tests/hana/test_intermout_always_comb_4_test.v b/tests/hana/test_intermout_always_comb_4_test.v deleted file mode 100644 index b0a94f299..000000000 --- a/tests/hana/test_intermout_always_comb_4_test.v +++ /dev/null @@ -1,9 +0,0 @@ -module test(a, b, c); -input b, c; -output reg a; - -always @(b or c) begin -a = b; -a = c; -end -endmodule diff --git a/tests/hana/test_intermout_always_comb_5_test.v b/tests/hana/test_intermout_always_comb_5_test.v deleted file mode 100644 index 5152781df..000000000 --- a/tests/hana/test_intermout_always_comb_5_test.v +++ /dev/null @@ -1,11 +0,0 @@ -module test(ctrl, in1, in2, out); -input ctrl; -input in1, in2; -output reg out; - -always @ (ctrl or in1 or in2) - if(ctrl) - out = in1 & in2; - else - out = in1 | in2; -endmodule diff --git a/tests/hana/test_intermout_always_ff_3_test.v b/tests/hana/test_intermout_always_ff_3_test.v deleted file mode 100644 index ed8630c37..000000000 --- a/tests/hana/test_intermout_always_ff_3_test.v +++ /dev/null @@ -1,15 +0,0 @@ -module NonBlockingEx(clk, merge, er, xmit, fddi, claim); -input clk, merge, er, xmit, fddi; -output reg claim; -reg fcr; - -always @(posedge clk) -begin - fcr = er | xmit; - - if(merge) - claim = fcr & fddi; - else - claim = fddi; -end -endmodule diff --git a/tests/hana/test_intermout_always_ff_4_test.v b/tests/hana/test_intermout_always_ff_4_test.v deleted file mode 100644 index cac420a47..000000000 --- a/tests/hana/test_intermout_always_ff_4_test.v +++ /dev/null @@ -1,11 +0,0 @@ -module FlipFlop(clk, cs, ns); -input clk; -input [31:0] cs; -output [31:0] ns; -integer is; - -always @(posedge clk) - is <= cs; - -assign ns = is; -endmodule diff --git a/tests/hana/test_intermout_always_ff_5_test.v b/tests/hana/test_intermout_always_ff_5_test.v deleted file mode 100644 index 669b2a5f9..000000000 --- a/tests/hana/test_intermout_always_ff_5_test.v +++ /dev/null @@ -1,13 +0,0 @@ -module FlipFlop(clock, cs, ns); -input clock; -input [3:0] cs; -output reg [3:0] ns; -reg [3:0] temp; - -always @(posedge clock) -begin - temp = cs; - ns = temp; -end - -endmodule diff --git a/tests/hana/test_intermout_always_ff_6_test.v b/tests/hana/test_intermout_always_ff_6_test.v deleted file mode 100644 index ad0a0df6e..000000000 --- a/tests/hana/test_intermout_always_ff_6_test.v +++ /dev/null @@ -1,7 +0,0 @@ -module inc(clock, counter); - -input clock; -output reg [3:0] counter; -always @(posedge clock) - counter <= counter + 1; -endmodule diff --git a/tests/hana/test_intermout_always_ff_8_test.v b/tests/hana/test_intermout_always_ff_8_test.v deleted file mode 100644 index 0f29ea0a4..000000000 --- a/tests/hana/test_intermout_always_ff_8_test.v +++ /dev/null @@ -1,11 +0,0 @@ -module NegEdgeClock(q, d, clk, reset); -input d, clk, reset; -output reg q; - -always @(negedge clk or negedge reset) - if(!reset) - q <= 1'b0; - else - q <= d; - -endmodule diff --git a/tests/hana/test_intermout_always_ff_9_test.v b/tests/hana/test_intermout_always_ff_9_test.v deleted file mode 100644 index f1f13bbe7..000000000 --- a/tests/hana/test_intermout_always_ff_9_test.v +++ /dev/null @@ -1,14 +0,0 @@ -module MyCounter (clock, preset, updown, presetdata, counter); -input clock, preset, updown; -input [1: 0] presetdata; -output reg [1:0] counter; - -always @(posedge clock) - if(preset) - counter <= presetdata; - else - if(updown) - counter <= counter + 1; - else - counter <= counter - 1; -endmodule diff --git a/tests/hana/test_intermout_always_latch_1_test.v b/tests/hana/test_intermout_always_latch_1_test.v deleted file mode 100644 index a83be20d1..000000000 --- a/tests/hana/test_intermout_always_latch_1_test.v +++ /dev/null @@ -1,9 +0,0 @@ -module test(en, in, out); -input en; -input [1:0] in; -output reg [2:0] out; - -always @ (en or in) - if(en) - out = in + 1; -endmodule diff --git a/tests/hana/test_intermout_bufrm_1_test.v b/tests/hana/test_intermout_bufrm_1_test.v deleted file mode 100644 index 8e3d4222e..000000000 --- a/tests/hana/test_intermout_bufrm_1_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input in, output out); -//no buffer removal -assign out = in; -endmodule diff --git a/tests/hana/test_intermout_bufrm_2_test.v b/tests/hana/test_intermout_bufrm_2_test.v deleted file mode 100644 index 853f1dc9a..000000000 --- a/tests/hana/test_intermout_bufrm_2_test.v +++ /dev/null @@ -1,7 +0,0 @@ -module test(input in, output out); -//intermediate buffers should be removed -wire w1, w2; -assign w1 = in; -assign w2 = w1; -assign out = w2; -endmodule diff --git a/tests/hana/test_intermout_bufrm_6_test.v b/tests/hana/test_intermout_bufrm_6_test.v deleted file mode 100644 index d4f3878d5..000000000 --- a/tests/hana/test_intermout_bufrm_6_test.v +++ /dev/null @@ -1,22 +0,0 @@ -module test(in, out); -input in; -output out; - -wire w1, w2, w3, w4; -assign w1 = in; -assign w2 = w1; -assign w4 = w3; -assign out = w4; -mybuf _mybuf(w2, w3); -endmodule - -module mybuf(in, out); -input in; -output out; -wire w1, w2, w3, w4; - -assign w1 = in; -assign w2 = w1; -assign out = w2; -endmodule - diff --git a/tests/hana/test_intermout_bufrm_7_test.v b/tests/hana/test_intermout_bufrm_7_test.v deleted file mode 100644 index 7b651302a..000000000 --- a/tests/hana/test_intermout_bufrm_7_test.v +++ /dev/null @@ -1,33 +0,0 @@ -module test(in1, in2, out); -input in1, in2; -output out; -// Y with cluster of mybuf instances at the junction - -wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10; -assign w1 = in1; -assign w2 = w1; -assign w5 = in2; -assign w6 = w5; -assign w10 = w9; -assign out = w10; - -mybuf _mybuf0(w2, w3); -mybuf _mybuf1(w3, w4); - -mybuf _mybuf2(w6, w7); -mybuf _mybuf3(w7, w4); - -mybuf _mybuf4(w4, w8); -mybuf _mybuf5(w8, w9); -endmodule - -module mybuf(in, out); -input in; -output out; -wire w1, w2, w3, w4; - -assign w1 = in; -assign w2 = w1; -assign out = w2; -endmodule - diff --git a/tests/hana/test_intermout_exprs_add_test.v b/tests/hana/test_intermout_exprs_add_test.v deleted file mode 100644 index ec70f347b..000000000 --- a/tests/hana/test_intermout_exprs_add_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test(out, in1, in2, vin1, vin2, vout1); -output out; -input in1, in2; -input [1:0] vin1; -input [2:0] vin2; -output [3:0] vout1; - -assign out = in1 + in2; -assign vout1 = vin1 + vin2; -endmodule diff --git a/tests/hana/test_intermout_exprs_binlogic_test.v b/tests/hana/test_intermout_exprs_binlogic_test.v deleted file mode 100644 index eec8c4b1a..000000000 --- a/tests/hana/test_intermout_exprs_binlogic_test.v +++ /dev/null @@ -1,13 +0,0 @@ -module test(in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1 ); -input in1, in2; -input [1:0] vin1; -input [3:0] vin2; -input [1:0] vin3; -input [3:0] vin4; -output vout, vout1; -output out; - -assign out = in1 && in2; -assign vout = vin1 && vin2; -assign vout1 = vin3 || vin4; -endmodule diff --git a/tests/hana/test_intermout_exprs_bitwiseneg_test.v b/tests/hana/test_intermout_exprs_bitwiseneg_test.v deleted file mode 100644 index 5b62bef09..000000000 --- a/tests/hana/test_intermout_exprs_bitwiseneg_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(output out, input in, output [1:0] vout, input [1:0] vin); - -assign out = ~in; -assign vout = ~vin; -endmodule diff --git a/tests/hana/test_intermout_exprs_buffer_test.v b/tests/hana/test_intermout_exprs_buffer_test.v deleted file mode 100644 index 2b4cbc3ed..000000000 --- a/tests/hana/test_intermout_exprs_buffer_test.v +++ /dev/null @@ -1,9 +0,0 @@ -module buffer(in, out, vin, vout); -input in; -output out; -input [1:0] vin; -output [1:0] vout; - -assign out = in; -assign vout = vin; -endmodule diff --git a/tests/hana/test_intermout_exprs_condexpr_mux_test.v b/tests/hana/test_intermout_exprs_condexpr_mux_test.v deleted file mode 100644 index 11006e8b3..000000000 --- a/tests/hana/test_intermout_exprs_condexpr_mux_test.v +++ /dev/null @@ -1,11 +0,0 @@ -module test(in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2); -input in1, in2, en1, ven1; -input [1:0] ven2; -output out; -input [1:0] vin1, vin2, vin3, vin4; -output [1:0] vout1, vout2; - -assign out = en1 ? in1 : in2; -assign vout1 = ven1 ? vin1 : vin2; -assign vout2 = ven2 ? vin3 : vin4; -endmodule diff --git a/tests/hana/test_intermout_exprs_condexpr_tribuf_test.v b/tests/hana/test_intermout_exprs_condexpr_tribuf_test.v deleted file mode 100644 index 5b778fe98..000000000 --- a/tests/hana/test_intermout_exprs_condexpr_tribuf_test.v +++ /dev/null @@ -1,9 +0,0 @@ -module test(in, out, en, vin1, vout1, en1); -input in, en, en1; -output out; -input [1:0] vin1; -output [1:0] vout1; - -assign out = en ? in : 1'bz; -assign vout1 = en1 ? vin1 : 2'bzz; -endmodule diff --git a/tests/hana/test_intermout_exprs_const_test.v b/tests/hana/test_intermout_exprs_const_test.v deleted file mode 100644 index 484d81032..000000000 --- a/tests/hana/test_intermout_exprs_const_test.v +++ /dev/null @@ -1,7 +0,0 @@ -module test (out, vout); -output out; -output [7:0] vout; - -assign out = 1'b1; -assign vout = 9; -endmodule diff --git a/tests/hana/test_intermout_exprs_constshift_test.v b/tests/hana/test_intermout_exprs_constshift_test.v deleted file mode 100644 index eb21315d7..000000000 --- a/tests/hana/test_intermout_exprs_constshift_test.v +++ /dev/null @@ -1,12 +0,0 @@ -module test(in, out, vin, vout, vin1, vout1, vin2, vout2); - -input in; -input [3:0] vin, vin1, vin2; -output [3:0] vout, vout1, vout2; -output out; - -assign out = in << 1; -assign vout = vin << 2; -assign vout1 = vin1 >> 2; -assign vout2 = vin2 >>> 2; -endmodule diff --git a/tests/hana/test_intermout_exprs_div_test.v b/tests/hana/test_intermout_exprs_div_test.v deleted file mode 100644 index 21765fcdf..000000000 --- a/tests/hana/test_intermout_exprs_div_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test(out, in1, in2, vin1, vin2, vout1); -output out; -input in1, in2; -input [1:0] vin1; -input [2:0] vin2; -output [3:0] vout1; - -assign out = in1 / in2; -assign vout1 = vin1 / vin2; -endmodule diff --git a/tests/hana/test_intermout_exprs_logicneg_test.v b/tests/hana/test_intermout_exprs_logicneg_test.v deleted file mode 100644 index b45b32b9c..000000000 --- a/tests/hana/test_intermout_exprs_logicneg_test.v +++ /dev/null @@ -1,7 +0,0 @@ -module test(out, vout, in, vin); -output out, vout; -input in; -input [3:0] vin; -assign out = !in; -assign vout = !vin; -endmodule diff --git a/tests/hana/test_intermout_exprs_mod_test.v b/tests/hana/test_intermout_exprs_mod_test.v deleted file mode 100644 index cea6b02d7..000000000 --- a/tests/hana/test_intermout_exprs_mod_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test(out, in1, in2, vin1, vin2, vout1); -output out; -input in1, in2; -input [1:0] vin1; -input [2:0] vin2; -output [3:0] vout1; - -assign out = in1 % in2; -assign vout1 = vin1 % vin2; -endmodule diff --git a/tests/hana/test_intermout_exprs_mul_test.v b/tests/hana/test_intermout_exprs_mul_test.v deleted file mode 100644 index f9973dadc..000000000 --- a/tests/hana/test_intermout_exprs_mul_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test(out, in1, in2, vin1, vin2, vout1); -output out; -input in1, in2; -input [1:0] vin1; -input [2:0] vin2; -output [3:0] vout1; - -assign out = in1 * in2; -assign vout1 = vin1 * vin2; -endmodule diff --git a/tests/hana/test_intermout_exprs_redand_test.v b/tests/hana/test_intermout_exprs_redand_test.v deleted file mode 100644 index 35fdf73ac..000000000 --- a/tests/hana/test_intermout_exprs_redand_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(output out, input [1:0] vin, output out1, input [3:0] vin1); - -assign out = &vin; -assign out1 = &vin1; -endmodule diff --git a/tests/hana/test_intermout_exprs_redop_test.v b/tests/hana/test_intermout_exprs_redop_test.v deleted file mode 100644 index 93fdb2e57..000000000 --- a/tests/hana/test_intermout_exprs_redop_test.v +++ /dev/null @@ -1,16 +0,0 @@ -module Reduction (A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6); -input [1:0] A1; -input [1:0] A2; -input [1:0] A3; -input [1:0] A4; -input [1:0] A5; -input [1:0] A6; -output Y1, Y2, Y3, Y4, Y5, Y6; -//reg Y1, Y2, Y3, Y4, Y5, Y6; -assign Y1=&A1; //reduction AND -assign Y2=|A2; //reduction OR -assign Y3=~&A3; //reduction NAND -assign Y4=~|A4; //reduction NOR -assign Y5=^A5; //reduction XOR -assign Y6=~^A6; //reduction XNOR -endmodule diff --git a/tests/hana/test_intermout_exprs_sub_test.v b/tests/hana/test_intermout_exprs_sub_test.v deleted file mode 100644 index 06e3a8149..000000000 --- a/tests/hana/test_intermout_exprs_sub_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test(out, in1, in2, vin1, vin2, vout1); -output out; -input in1, in2; -input [1:0] vin1; -input [2:0] vin2; -output [3:0] vout1; - -assign out = in1 - in2; -assign vout1 = vin1 - vin2; -endmodule diff --git a/tests/hana/test_intermout_exprs_unaryminus_test.v b/tests/hana/test_intermout_exprs_unaryminus_test.v deleted file mode 100644 index ee3f229a8..000000000 --- a/tests/hana/test_intermout_exprs_unaryminus_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(output out, input in, output [31:0] vout, input [31:0] vin); - -assign out = -in; -assign vout = -vin; -endmodule diff --git a/tests/hana/test_intermout_exprs_unaryplus_test.v b/tests/hana/test_intermout_exprs_unaryplus_test.v deleted file mode 100644 index 07be5b240..000000000 --- a/tests/hana/test_intermout_exprs_unaryplus_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(output out, input in); - -assign out = +in; -endmodule diff --git a/tests/hana/test_intermout_exprs_varshift_test.v b/tests/hana/test_intermout_exprs_varshift_test.v deleted file mode 100644 index 2ca35c091..000000000 --- a/tests/hana/test_intermout_exprs_varshift_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test(vin0, vout0); -input [2:0] vin0; -output reg [7:0] vout0; - -wire [7:0] myreg0, myreg1, myreg2; -integer i; -assign myreg0 = vout0 << vin0; - -assign myreg1 = myreg2 >> i; -endmodule diff --git a/tests/hana/test_parse2synthtrans.v b/tests/hana/test_parse2synthtrans.v new file mode 100644 index 000000000..a1c0bfdb8 --- /dev/null +++ b/tests/hana/test_parse2synthtrans.v @@ -0,0 +1,117 @@ + +// test_parse2synthtrans_behavopt_1_test.v +module f1_test(in, out, clk, reset); +input in, reset; +output reg out; +input clk; +reg signed [3:0] a; +reg signed [3:0] b; +reg signed [3:0] c; +reg [5:0] d; +reg [5:0] e; + +always @(clk or reset) begin + a = -4; + b = 2; + c = a + b; + d = a + b + c; + d = d*d; + if(b) + e = d*d; + else + e = d + d; +end +endmodule + +// test_parse2synthtrans_case_1_test.v +module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0); +output out0, out1, out2, out3; +reg out0, out1, out2, out3; +input in; +input s1, s0; +reg [3:0] encoding; +reg [1:0] state; + always @(encoding) begin + case (encoding) + 4'bxx11: state = 1; + 4'bx0xx: state = 3; + 4'b11xx: state = 4; + 4'bx1xx: state = 2; + 4'bxx1x: state = 1; + 4'bxxx1: state = 0; + default: state = 0; + endcase + end + + always @(encoding) begin + case (encoding) + 4'b0000: state = 1; + default: state = 0; + endcase + end +endmodule + +// test_parse2synthtrans_contassign_1_test.v +module f3_test(in, out); + +input wire in; +output out; +assign out = (in+in); +assign out = 74; +endmodule + +// test_parse2synthtrans_module_basic0_test.v +module f4_test; +endmodule + +// test_parse2synthtrans_operators_1_test.v +module f5_test(in, out); +input in; +output out; +parameter p1 = 10; +parameter p2 = 5; + +assign out = +p1; +assign out = -p2; +assign out = p1 + p2; +assign out = p1 - p2; +endmodule + +// test_parse2synthtrans_param_1_test.v +module f6_test(in, out); +input in; +output out; +parameter p = 10; + +assign out = p; +endmodule + +// test_parse2synthtrans_port_scalar_1_test.v +module f7_test(in, out, io); +inout io; +output out; +input in; + +endmodule + +// test_parse2synthtrans_port_vector_1_test.v +module f8_test(in1, in2, out1, out2, io1, io2); +inout [1:0] io1; +inout [0:1] io2; +output [1:0] out1; +output [0:1] out2; +input [1:0] in1; +input [0:1] in2; + +endmodule + +// test_parse2synthtrans_v2k_comb_logic_sens_list_test.v +module f9_test(q, d, clk, reset); +output reg q; +input d, clk, reset; + +always @ (posedge clk, negedge reset) + if(!reset) q <= 0; + else q <= d; + +endmodule diff --git a/tests/hana/test_parse2synthtrans_behavopt_1_test.v b/tests/hana/test_parse2synthtrans_behavopt_1_test.v deleted file mode 100644 index c825739c6..000000000 --- a/tests/hana/test_parse2synthtrans_behavopt_1_test.v +++ /dev/null @@ -1,22 +0,0 @@ -module test(in, out, clk, reset); -input in, reset; -output reg out; -input clk; -reg signed [3:0] a; -reg signed [3:0] b; -reg signed [3:0] c; -reg [5:0] d; -reg [5:0] e; - -always @(clk or reset) begin - a = -4; - b = 2; - c = a + b; - d = a + b + c; - d = d*d; - if(b) - e = d*d; - else - e = d + d; -end -endmodule diff --git a/tests/hana/test_parse2synthtrans_case_1_test.v b/tests/hana/test_parse2synthtrans_case_1_test.v deleted file mode 100644 index 348c566ad..000000000 --- a/tests/hana/test_parse2synthtrans_case_1_test.v +++ /dev/null @@ -1,26 +0,0 @@ -module demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0); -output out0, out1, out2, out3; -reg out0, out1, out2, out3; -input in; -input s1, s0; -reg [3:0] encoding; -reg [1:0] state; - always @(encoding) begin - case (encoding) - 4'bxx11: state = 1; - 4'bx0xx: state = 3; - 4'b11xx: state = 4; - 4'bx1xx: state = 2; - 4'bxx1x: state = 1; - 4'bxxx1: state = 0; - default: state = 0; - endcase - end - - always @(encoding) begin - case (encoding) - 4'b0000: state = 1; - default: state = 0; - endcase - end -endmodule diff --git a/tests/hana/test_parse2synthtrans_contassign_1_test.v b/tests/hana/test_parse2synthtrans_contassign_1_test.v deleted file mode 100644 index 78bf00775..000000000 --- a/tests/hana/test_parse2synthtrans_contassign_1_test.v +++ /dev/null @@ -1,7 +0,0 @@ -module test(in, out); - -input wire in; -output out; -assign out = (in+in); -assign out = 74; -endmodule diff --git a/tests/hana/test_parse2synthtrans_module_basic0_test.v b/tests/hana/test_parse2synthtrans_module_basic0_test.v deleted file mode 100644 index 67a272df0..000000000 --- a/tests/hana/test_parse2synthtrans_module_basic0_test.v +++ /dev/null @@ -1,2 +0,0 @@ -module test; -endmodule diff --git a/tests/hana/test_parse2synthtrans_operators_1_test.v b/tests/hana/test_parse2synthtrans_operators_1_test.v deleted file mode 100644 index 93b5691f3..000000000 --- a/tests/hana/test_parse2synthtrans_operators_1_test.v +++ /dev/null @@ -1,11 +0,0 @@ -module test(in, out); -input in; -output out; -parameter p1 = 10; -parameter p2 = 5; - -assign out = +p1; -assign out = -p2; -assign out = p1 + p2; -assign out = p1 - p2; -endmodule diff --git a/tests/hana/test_parse2synthtrans_param_1_test.v b/tests/hana/test_parse2synthtrans_param_1_test.v deleted file mode 100644 index 146eedf42..000000000 --- a/tests/hana/test_parse2synthtrans_param_1_test.v +++ /dev/null @@ -1,7 +0,0 @@ -module test(in, out); -input in; -output out; -parameter p = 10; - -assign out = p; -endmodule diff --git a/tests/hana/test_parse2synthtrans_port_scalar_1_test.v b/tests/hana/test_parse2synthtrans_port_scalar_1_test.v deleted file mode 100644 index 8cdf495a0..000000000 --- a/tests/hana/test_parse2synthtrans_port_scalar_1_test.v +++ /dev/null @@ -1,6 +0,0 @@ -module test(in, out, io); -inout io; -output out; -input in; - -endmodule diff --git a/tests/hana/test_parse2synthtrans_port_vector_1_test.v b/tests/hana/test_parse2synthtrans_port_vector_1_test.v deleted file mode 100644 index a740282b3..000000000 --- a/tests/hana/test_parse2synthtrans_port_vector_1_test.v +++ /dev/null @@ -1,9 +0,0 @@ -module test(in1, in2, out1, out2, io1, io2); -inout [1:0] io1; -inout [0:1] io2; -output [1:0] out1; -output [0:1] out2; -input [1:0] in1; -input [0:1] in2; - -endmodule diff --git a/tests/hana/test_parse2synthtrans_v2k_comb_logic_sens_list_test.v b/tests/hana/test_parse2synthtrans_v2k_comb_logic_sens_list_test.v deleted file mode 100644 index 50f1d3531..000000000 --- a/tests/hana/test_parse2synthtrans_v2k_comb_logic_sens_list_test.v +++ /dev/null @@ -1,9 +0,0 @@ -module test(q, d, clk, reset); -output reg q; -input d, clk, reset; - -always @ (posedge clk, negedge reset) - if(!reset) q <= 0; - else q <= d; - -endmodule diff --git a/tests/hana/test_parser.v b/tests/hana/test_parser.v new file mode 100644 index 000000000..c7305356a --- /dev/null +++ b/tests/hana/test_parser.v @@ -0,0 +1,87 @@ + +// test_parser_constructs_module_basic1_test.v +module f1_test; +endmodule + +// test_parser_constructs_param_basic0_test.v +module f2_test #( parameter v2kparam = 5) +(in, out, io, vin, vout, vio); +input in; +output out; +inout io; +input [3:0] vin; +output [v2kparam:0] vout; +inout [0:3] vio; +parameter myparam = 10; +endmodule + +// test_parser_constructs_port_basic0_test.v +module f3_test(in, out, io, vin, vout, vio); +input in; +output out; +inout io; +input [3:0] vin; +output [3:0] vout; +inout [0:3] vio; +endmodule + +// test_parser_directives_define_simpledef_test.v +`define parvez ahmad +`define WIRE wire +`define TEN 10 + +module f4_`parvez(); +parameter param = `TEN; +`WIRE w; +assign w = `TEN; +endmodule + +// test_parser_misc_operators_test.v +module f5_test(out, i0, i1, i2, i3, s1, s0); +output out; +input i0, i1, i2, i3; +input s1, s0; + +assign out = (~s1 & s0 & i0) | + (~s1 & s0 & i1) | + (s1 & ~s0 & i2) | + (s1 & s0 & i3); + +endmodule + +module f5_ternaryop(out, i0, i1, i2, i3, s1, s0); +output out; +input i0, i1, i2, i3; +input s1, s0; + +assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0); + +endmodule + +module f5_fulladd4(sum, c_out, a, b, c_in); +output [3:0] sum; +output c_out; +input [3:0] a, b; +input c_in; + +assign {c_out, sum} = a + b + c_in; +endmodule + +// test_parser_v2k_comb_port_data_type_test.v +module f6_adder(sum , co, a, b, ci); +output reg [31:0] sum; +output reg co; +input wire [31:0] a, b; +input wire ci; +endmodule + +// test_parser_v2k_comma_sep_sens_list_test.v +module f7_test(q, d, clk, reset); +output reg q; +input d, clk, reset; + +always @ (posedge clk, negedge reset) + if(!reset) q <= 0; + else q <= d; + +endmodule diff --git a/tests/hana/test_parser_constructs_module_basic1_test.v b/tests/hana/test_parser_constructs_module_basic1_test.v deleted file mode 100644 index 67a272df0..000000000 --- a/tests/hana/test_parser_constructs_module_basic1_test.v +++ /dev/null @@ -1,2 +0,0 @@ -module test; -endmodule diff --git a/tests/hana/test_parser_constructs_param_basic0_test.v b/tests/hana/test_parser_constructs_param_basic0_test.v deleted file mode 100644 index fd679230e..000000000 --- a/tests/hana/test_parser_constructs_param_basic0_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test #( parameter v2kparam = 5) -(in, out, io, vin, vout, vio); -input in; -output out; -inout io; -input [3:0] vin; -output [v2kparam:0] vout; -inout [0:3] vio; -parameter myparam = 10; -endmodule diff --git a/tests/hana/test_parser_constructs_port_basic0_test.v b/tests/hana/test_parser_constructs_port_basic0_test.v deleted file mode 100644 index 8478e31da..000000000 --- a/tests/hana/test_parser_constructs_port_basic0_test.v +++ /dev/null @@ -1,8 +0,0 @@ -module test(in, out, io, vin, vout, vio); -input in; -output out; -inout io; -input [3:0] vin; -output [3:0] vout; -inout [0:3] vio; -endmodule diff --git a/tests/hana/test_parser_directives_define_simpledef_test.v b/tests/hana/test_parser_directives_define_simpledef_test.v deleted file mode 100644 index 4a5d2345c..000000000 --- a/tests/hana/test_parser_directives_define_simpledef_test.v +++ /dev/null @@ -1,9 +0,0 @@ -`define parvez ahmad -`define WIRE wire -`define TEN 10 - -module `parvez(); -parameter param = `TEN; -`WIRE w; -assign w = `TEN; -endmodule diff --git a/tests/hana/test_parser_misc_operators_test.v b/tests/hana/test_parser_misc_operators_test.v deleted file mode 100644 index 8fe8e7bad..000000000 --- a/tests/hana/test_parser_misc_operators_test.v +++ /dev/null @@ -1,29 +0,0 @@ -module test(out, i0, i1, i2, i3, s1, s0); -output out; -input i0, i1, i2, i3; -input s1, s0; - -assign out = (~s1 & s0 & i0) | - (~s1 & s0 & i1) | - (s1 & ~s0 & i2) | - (s1 & s0 & i3); - -endmodule - -module ternaryop(out, i0, i1, i2, i3, s1, s0); -output out; -input i0, i1, i2, i3; -input s1, s0; - -assign out = s1 ? (s0 ? i3 : i2) : (s0 ? i1 : i0); - -endmodule - -module fulladd4(sum, c_out, a, b, c_in); -output [3:0] sum; -output c_out; -input [3:0] a, b; -input c_in; - -assign {c_out, sum} = a + b + c_in; -endmodule diff --git a/tests/hana/test_parser_v2k_comb_port_data_type_test.v b/tests/hana/test_parser_v2k_comb_port_data_type_test.v deleted file mode 100644 index 099585b56..000000000 --- a/tests/hana/test_parser_v2k_comb_port_data_type_test.v +++ /dev/null @@ -1,6 +0,0 @@ -module adder(sum , co, a, b, ci); -output reg [31:0] sum; -output reg co; -input wire [31:0] a, b; -input wire ci; -endmodule diff --git a/tests/hana/test_parser_v2k_comma_sep_sens_list_test.v b/tests/hana/test_parser_v2k_comma_sep_sens_list_test.v deleted file mode 100644 index 50f1d3531..000000000 --- a/tests/hana/test_parser_v2k_comma_sep_sens_list_test.v +++ /dev/null @@ -1,9 +0,0 @@ -module test(q, d, clk, reset); -output reg q; -input d, clk, reset; - -always @ (posedge clk, negedge reset) - if(!reset) q <= 0; - else q <= d; - -endmodule diff --git a/tests/hana/test_simulation_always.v b/tests/hana/test_simulation_always.v new file mode 100644 index 000000000..3ee75313a --- /dev/null +++ b/tests/hana/test_simulation_always.v @@ -0,0 +1,135 @@ + +// test_simulation_always_15_test.v +module f1_test(input [1:0] in, output reg [1:0] out); + +always @(in) + out = in; +endmodule + +// test_simulation_always_17_test.v +module f2_test(a, b, c, d, z); +input a, b, c, d; +output z; +reg z, temp1, temp2; + +always @(a or b or c or d) +begin + temp1 = a ^ b; + temp2 = c ^ d; + z = temp1 ^ temp2; +end + +endmodule + +// test_simulation_always_18_test.v +module f3_test (in1, in2, out); +input in1, in2; +output reg out; + +always @ ( in1 or in2) + if(in1 > in2) + out = in1; + else + out = in2; +endmodule + +// test_simulation_always_19_test.v +module f4_test(ctrl, in1, in2, out); +input ctrl; +input in1, in2; +output reg out; + +always @ (ctrl or in1 or in2) + if(ctrl) + out = in1 & in2; + else + out = in1 | in2; +endmodule + +// test_simulation_always_1_test.v +module f5_test(input in, output reg out); + +always @(in) + out = in; +endmodule + +// test_simulation_always_20_test.v +module f6_NonBlockingEx(clk, merge, er, xmit, fddi, claim); +input clk, merge, er, xmit, fddi; +output reg claim; +reg fcr; + +always @(posedge clk) +begin + fcr <= er | xmit; + + if(merge) + claim <= fcr & fddi; + else + claim <= fddi; +end +endmodule + +// test_simulation_always_21_test.v +module f7_FlipFlop(clk, cs, ns); +input clk; +input [7:0] cs; +output [7:0] ns; +integer is; + +always @(posedge clk) + is <= cs; + +assign ns = is; +endmodule + +// test_simulation_always_22_test.v +module f8_inc(clock, counter); + +input clock; +output reg [7:0] counter; +always @(posedge clock) + counter <= counter + 1; +endmodule + +// test_simulation_always_23_test.v +module f9_MyCounter (clock, preset, updown, presetdata, counter); +input clock, preset, updown; +input [1: 0] presetdata; +output reg [1:0] counter; + +always @(posedge clock) + if(preset) + counter <= presetdata; + else + if(updown) + counter <= counter + 1; + else + counter <= counter - 1; +endmodule + +// test_simulation_always_27_test.v +module f10_FlipFlop(clock, cs, ns); +input clock; +input cs; +output reg ns; +reg temp; + +always @(posedge clock) +begin + temp <= cs; + ns <= temp; +end + +endmodule + +// test_simulation_always_29_test.v +module f11_test(input in, output reg [1:0] out); + + always @(in) + begin + out = in; + out = out + in; + end + +endmodule diff --git a/tests/hana/test_simulation_always_15_test.v b/tests/hana/test_simulation_always_15_test.v deleted file mode 100644 index 5c5fed5b6..000000000 --- a/tests/hana/test_simulation_always_15_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input [1:0] in, output reg [1:0] out); - -always @(in) - out = in; -endmodule diff --git a/tests/hana/test_simulation_always_17_test.v b/tests/hana/test_simulation_always_17_test.v deleted file mode 100644 index 2d5abc4a6..000000000 --- a/tests/hana/test_simulation_always_17_test.v +++ /dev/null @@ -1,13 +0,0 @@ -module test(a, b, c, d, z); -input a, b, c, d; -output z; -reg z, temp1, temp2; - -always @(a or b or c or d) -begin - temp1 = a ^ b; - temp2 = c ^ d; - z = temp1 ^ temp2; -end - -endmodule diff --git a/tests/hana/test_simulation_always_18_test.v b/tests/hana/test_simulation_always_18_test.v deleted file mode 100644 index 234407efd..000000000 --- a/tests/hana/test_simulation_always_18_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test (in1, in2, out); -input in1, in2; -output reg out; - -always @ ( in1 or in2) - if(in1 > in2) - out = in1; - else - out = in2; -endmodule diff --git a/tests/hana/test_simulation_always_19_test.v b/tests/hana/test_simulation_always_19_test.v deleted file mode 100644 index 5152781df..000000000 --- a/tests/hana/test_simulation_always_19_test.v +++ /dev/null @@ -1,11 +0,0 @@ -module test(ctrl, in1, in2, out); -input ctrl; -input in1, in2; -output reg out; - -always @ (ctrl or in1 or in2) - if(ctrl) - out = in1 & in2; - else - out = in1 | in2; -endmodule diff --git a/tests/hana/test_simulation_always_1_test.v b/tests/hana/test_simulation_always_1_test.v deleted file mode 100644 index 211369cb6..000000000 --- a/tests/hana/test_simulation_always_1_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input in, output reg out); - -always @(in) - out = in; -endmodule diff --git a/tests/hana/test_simulation_always_20_test.v b/tests/hana/test_simulation_always_20_test.v deleted file mode 100644 index 6b3e861dc..000000000 --- a/tests/hana/test_simulation_always_20_test.v +++ /dev/null @@ -1,15 +0,0 @@ -module NonBlockingEx(clk, merge, er, xmit, fddi, claim); -input clk, merge, er, xmit, fddi; -output reg claim; -reg fcr; - -always @(posedge clk) -begin - fcr <= er | xmit; - - if(merge) - claim <= fcr & fddi; - else - claim <= fddi; -end -endmodule diff --git a/tests/hana/test_simulation_always_21_test.v b/tests/hana/test_simulation_always_21_test.v deleted file mode 100644 index 6c47b4bdf..000000000 --- a/tests/hana/test_simulation_always_21_test.v +++ /dev/null @@ -1,11 +0,0 @@ -module FlipFlop(clk, cs, ns); -input clk; -input [7:0] cs; -output [7:0] ns; -integer is; - -always @(posedge clk) - is <= cs; - -assign ns = is; -endmodule diff --git a/tests/hana/test_simulation_always_22_test.v b/tests/hana/test_simulation_always_22_test.v deleted file mode 100644 index 8d91f8154..000000000 --- a/tests/hana/test_simulation_always_22_test.v +++ /dev/null @@ -1,7 +0,0 @@ -module inc(clock, counter); - -input clock; -output reg [7:0] counter; -always @(posedge clock) - counter <= counter + 1; -endmodule diff --git a/tests/hana/test_simulation_always_23_test.v b/tests/hana/test_simulation_always_23_test.v deleted file mode 100644 index f1f13bbe7..000000000 --- a/tests/hana/test_simulation_always_23_test.v +++ /dev/null @@ -1,14 +0,0 @@ -module MyCounter (clock, preset, updown, presetdata, counter); -input clock, preset, updown; -input [1: 0] presetdata; -output reg [1:0] counter; - -always @(posedge clock) - if(preset) - counter <= presetdata; - else - if(updown) - counter <= counter + 1; - else - counter <= counter - 1; -endmodule diff --git a/tests/hana/test_simulation_always_27_test.v b/tests/hana/test_simulation_always_27_test.v deleted file mode 100644 index 577378fd6..000000000 --- a/tests/hana/test_simulation_always_27_test.v +++ /dev/null @@ -1,13 +0,0 @@ -module FlipFlop(clock, cs, ns); -input clock; -input cs; -output reg ns; -reg temp; - -always @(posedge clock) -begin - temp <= cs; - ns <= temp; -end - -endmodule diff --git a/tests/hana/test_simulation_always_29_test.v b/tests/hana/test_simulation_always_29_test.v deleted file mode 100644 index 55606832a..000000000 --- a/tests/hana/test_simulation_always_29_test.v +++ /dev/null @@ -1,9 +0,0 @@ -module test(input in, output reg [1:0] out); - - always @(in) - begin - out = in; - out = out + in; - end - -endmodule diff --git a/tests/hana/test_simulation_and.v b/tests/hana/test_simulation_and.v new file mode 100644 index 000000000..480e733d1 --- /dev/null +++ b/tests/hana/test_simulation_and.v @@ -0,0 +1,35 @@ + +// test_simulation_and_1_test.v +module f1_test(input [1:0] in, output out); +assign out = in[0] & in[1]; +endmodule + +// test_simulation_and_2_test.v +module f2_test(input [1:0] in, output out); +assign out = in[0] && in[1]; +endmodule + +// test_simulation_and_3_test.v +module f3_test(input [2:0] in, output out); +assign out = in[0] & in[1] & in[2]; +endmodule + +// test_simulation_and_4_test.v +module f4_test(input [2:0] in, output out); +assign out = in[0] && in[1] && in[2]; +endmodule + +// test_simulation_and_5_test.v +module f5_test(input [3:0] in, output out); +assign out = in[0] & in[1] & in[2] & in[3]; +endmodule + +// test_simulation_and_6_test.v +module f6_test(input [3:0] in, output out); +assign out = in[0] && in[1] && in[2] && in[3]; +endmodule + +// test_simulation_and_7_test.v +module f7_test(input [3:0] in, output out); +and myand(out, in[0], in[1], in[2], in[3]); +endmodule diff --git a/tests/hana/test_simulation_and_1_test.v b/tests/hana/test_simulation_and_1_test.v deleted file mode 100644 index fba639ca8..000000000 --- a/tests/hana/test_simulation_and_1_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, output out); -assign out = in[0] & in[1]; -endmodule diff --git a/tests/hana/test_simulation_and_2_test.v b/tests/hana/test_simulation_and_2_test.v deleted file mode 100644 index 715bc7ca6..000000000 --- a/tests/hana/test_simulation_and_2_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, output out); -assign out = in[0] && in[1]; -endmodule diff --git a/tests/hana/test_simulation_and_3_test.v b/tests/hana/test_simulation_and_3_test.v deleted file mode 100644 index 74dccabf8..000000000 --- a/tests/hana/test_simulation_and_3_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = in[0] & in[1] & in[2]; -endmodule diff --git a/tests/hana/test_simulation_and_4_test.v b/tests/hana/test_simulation_and_4_test.v deleted file mode 100644 index 48ed9102a..000000000 --- a/tests/hana/test_simulation_and_4_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = in[0] && in[1] && in[2]; -endmodule diff --git a/tests/hana/test_simulation_and_5_test.v b/tests/hana/test_simulation_and_5_test.v deleted file mode 100644 index 29a355786..000000000 --- a/tests/hana/test_simulation_and_5_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = in[0] & in[1] & in[2] & in[3]; -endmodule diff --git a/tests/hana/test_simulation_and_6_test.v b/tests/hana/test_simulation_and_6_test.v deleted file mode 100644 index ebce4eebf..000000000 --- a/tests/hana/test_simulation_and_6_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = in[0] && in[1] && in[2] && in[3]; -endmodule diff --git a/tests/hana/test_simulation_and_7_test.v b/tests/hana/test_simulation_and_7_test.v deleted file mode 100644 index d394adad7..000000000 --- a/tests/hana/test_simulation_and_7_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -and myand(out, in[0], in[1], in[2], in[3]); -endmodule diff --git a/tests/hana/test_simulation_buffer.v b/tests/hana/test_simulation_buffer.v new file mode 100644 index 000000000..d674b05ca --- /dev/null +++ b/tests/hana/test_simulation_buffer.v @@ -0,0 +1,17 @@ + +// test_simulation_buffer_1_test.v +module f1_test(input in, output out); +assign out = in; +endmodule + +// test_simulation_buffer_2_test.v +module f2_test(input [1:0] in, output [1:0] out); +assign out[0] = in[0]; +assign out[1] = in[1]; +endmodule + +// test_simulation_buffer_3_test.v +module f3_test(input in, output [1:0] out); +assign out[0] = in; +assign out[1] = in; +endmodule diff --git a/tests/hana/test_simulation_buffer_1_test.v b/tests/hana/test_simulation_buffer_1_test.v deleted file mode 100644 index e9bb7f617..000000000 --- a/tests/hana/test_simulation_buffer_1_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input in, output out); -assign out = in; -endmodule diff --git a/tests/hana/test_simulation_buffer_2_test.v b/tests/hana/test_simulation_buffer_2_test.v deleted file mode 100644 index 9a3f5aa3a..000000000 --- a/tests/hana/test_simulation_buffer_2_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [1:0] in, output [1:0] out); -assign out[0] = in[0]; -assign out[1] = in[1]; -endmodule diff --git a/tests/hana/test_simulation_buffer_3_test.v b/tests/hana/test_simulation_buffer_3_test.v deleted file mode 100644 index 9bca426d1..000000000 --- a/tests/hana/test_simulation_buffer_3_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input in, output [1:0] out); -assign out[0] = in; -assign out[1] = in; -endmodule diff --git a/tests/hana/test_simulation_decoder_8_test.v b/tests/hana/test_simulation_decoder.v index 751d60f67..ef9045aad 100644 --- a/tests/hana/test_simulation_decoder_8_test.v +++ b/tests/hana/test_simulation_decoder.v @@ -1,4 +1,147 @@ -module test (input [5:0] in, input enable, output reg [63:0] out); + +// test_simulation_decoder_2_test.v +module f1_test (input [1:0] in, input enable, output reg out); + +always @(in or enable) + if(!enable) + out = 4'b0000; + else begin + case (in) + 2'b00 : out = 0 ; + 2'b01 : out = 1; + 2'b10 : out = 0; + 2'b11 : out = 1; + endcase + end +endmodule + +// test_simulation_decoder_3_test.v +module f2_test (input [1:0] in, input enable, output reg [2:0] out); + +always @(in or enable) + if(!enable) + out = 3'b000; + else begin + case (in) + 2'b00 : out = 3'b001 ; + 2'b01 : out = 3'b010; + 2'b10 : out = 3'b010; + 2'b11 : out = 3'b100; + endcase + end +endmodule + +// test_simulation_decoder_4_test.v +module f3_test (input [2:0] in, output reg [7:0] out); + +always @(in ) + case (in) + 3'b000 : out = 8'b00000001; + 3'b001 : out = 8'b00000010; + 3'b010 : out = 8'b00000100; + 3'b011 : out = 8'b00001000; + 3'b100 : out = 8'b00010000; + 3'b101 : out = 8'b00100000; + 3'b110 : out = 8'b01000000; + 3'b111 : out = 8'b10000000; + endcase +endmodule + +// test_simulation_decoder_5_test.v +module f4_test (input [2:0] in, input enable, output reg [7:0] out); + +always @(in or enable ) + if(!enable) + out = 8'b00000000; + else + case (in) + 3'b000 : out = 8'b00000001; + 3'b001 : out = 8'b00000010; + 3'b010 : out = 8'b00000100; + 3'b011 : out = 8'b00001000; + 3'b100 : out = 8'b00010000; + 3'b101 : out = 8'b00100000; + 3'b110 : out = 8'b01000000; + 3'b111 : out = 8'b10000000; + endcase +endmodule + +// test_simulation_decoder_6_test.v +module f5_test (input [3:0] in, input enable, output reg [15:0] out); + +always @(in or enable) + if(!enable) + out = 16'b0000000000000000; + else begin + case (in) + 4'b0000 : out = 16'b0000000000000001; + 4'b0001 : out = 16'b0000000000000010; + 4'b0010 : out = 16'b0000000000000100; + 4'b0011 : out = 16'b0000000000001000; + 4'b0100 : out = 16'b0000000000010000; + 4'b0101 : out = 16'b0000000000100000; + 4'b0110 : out = 16'b0000000001000000; + 4'b0111 : out = 16'b0000000010000000; + 4'b1000 : out = 16'b0000000100000000; + 4'b1001 : out = 16'b0000001000000000; + 4'b1010 : out = 16'b0000010000000000; + 4'b1011 : out = 16'b0000100000000000; + 4'b1100 : out = 16'b0001000000000000; + 4'b1101 : out = 16'b0010000000000000; + 4'b1110 : out = 16'b0100000000000000; + 4'b1111 : out = 16'b1000000000000000; + endcase + end +endmodule + + +// test_simulation_decoder_7_test.v +module f6_test (input [4:0] in, input enable, output reg [31:0] out); + +always @(in or enable) + if(!enable) + out = 32'b00000000000000000000000000000000; + else begin + case (in) + 5'b00000 : out = 32'b00000000000000000000000000000001; + 5'b00001 : out = 32'b00000000000000000000000000000010; + 5'b00010 : out = 32'b00000000000000000000000000000100; + 5'b00011 : out = 32'b00000000000000000000000000001000; + 5'b00100 : out = 32'b00000000000000000000000000010000; + 5'b00101 : out = 32'b00000000000000000000000000100000; + 5'b00110 : out = 32'b00000000000000000000000001000000; + 5'b00111 : out = 32'b00000000000000000000000010000000; + 5'b01000 : out = 32'b00000000000000000000000100000000; + 5'b01001 : out = 32'b00000000000000000000001000000000; + 5'b01010 : out = 32'b00000000000000000000010000000000; + 5'b01011 : out = 32'b00000000000000000000100000000000; + 5'b01100 : out = 32'b00000000000000000001000000000000; + 5'b01101 : out = 32'b00000000000000000010000000000000; + 5'b01110 : out = 32'b00000000000000000100000000000000; + 5'b01111 : out = 32'b00000000000000001000000000000000; + 5'b10000 : out = 32'b00000000000000010000000000000000; + 5'b10001 : out = 32'b00000000000000100000000000000000; + 5'b10010 : out = 32'b00000000000001000000000000000000; + 5'b10011 : out = 32'b00000000000010000000000000000000; + 5'b10100 : out = 32'b00000000000100000000000000000000; + 5'b10101 : out = 32'b00000000001000000000000000000000; + 5'b10110 : out = 32'b00000000010000000000000000000000; + 5'b10111 : out = 32'b00000000100000000000000000000000; + 5'b11000 : out = 32'b00000001000000000000000000000000; + 5'b11001 : out = 32'b00000010000000000000000000000000; + 5'b11010 : out = 32'b00000100000000000000000000000000; + 5'b11011 : out = 32'b00001000000000000000000000000000; + 5'b11100 : out = 32'b00010000000000000000000000000000; + 5'b11101 : out = 32'b00100000000000000000000000000000; + 5'b11110 : out = 32'b01000000000000000000000000000000; + 5'b11111 : out = 32'b10000000000000000000000000000000; + endcase + end +endmodule + + +// test_simulation_decoder_8_test.v +module f7_test (input [5:0] in, input enable, output reg [63:0] out); always @(in or enable) if(!enable) diff --git a/tests/hana/test_simulation_decoder_2_test.v b/tests/hana/test_simulation_decoder_2_test.v deleted file mode 100644 index 5bdf19717..000000000 --- a/tests/hana/test_simulation_decoder_2_test.v +++ /dev/null @@ -1,14 +0,0 @@ -module test (input [1:0] in, input enable, output reg out); - -always @(in or enable) - if(!enable) - out = 4'b0000; - else begin - case (in) - 2'b00 : out = 0 ; - 2'b01 : out = 1; - 2'b10 : out = 0; - 2'b11 : out = 1; - endcase - end -endmodule diff --git a/tests/hana/test_simulation_decoder_3_test.v b/tests/hana/test_simulation_decoder_3_test.v deleted file mode 100644 index 44f5de12b..000000000 --- a/tests/hana/test_simulation_decoder_3_test.v +++ /dev/null @@ -1,14 +0,0 @@ -module test (input [1:0] in, input enable, output reg [2:0] out); - -always @(in or enable) - if(!enable) - out = 3'b000; - else begin - case (in) - 2'b00 : out = 3'b001 ; - 2'b01 : out = 3'b010; - 2'b10 : out = 3'b010; - 2'b11 : out = 3'b100; - endcase - end -endmodule diff --git a/tests/hana/test_simulation_decoder_4_test.v b/tests/hana/test_simulation_decoder_4_test.v deleted file mode 100644 index 871a5bbfd..000000000 --- a/tests/hana/test_simulation_decoder_4_test.v +++ /dev/null @@ -1,14 +0,0 @@ -module test (input [2:0] in, output reg [7:0] out); - -always @(in ) - case (in) - 3'b000 : out = 8'b00000001; - 3'b001 : out = 8'b00000010; - 3'b010 : out = 8'b00000100; - 3'b011 : out = 8'b00001000; - 3'b100 : out = 8'b00010000; - 3'b101 : out = 8'b00100000; - 3'b110 : out = 8'b01000000; - 3'b111 : out = 8'b10000000; - endcase -endmodule diff --git a/tests/hana/test_simulation_decoder_5_test.v b/tests/hana/test_simulation_decoder_5_test.v deleted file mode 100644 index 497fa4bfd..000000000 --- a/tests/hana/test_simulation_decoder_5_test.v +++ /dev/null @@ -1,17 +0,0 @@ -module test (input [2:0] in, input enable, output reg [7:0] out); - -always @(in or enable ) - if(!enable) - out = 8'b00000000; - else - case (in) - 3'b000 : out = 8'b00000001; - 3'b001 : out = 8'b00000010; - 3'b010 : out = 8'b00000100; - 3'b011 : out = 8'b00001000; - 3'b100 : out = 8'b00010000; - 3'b101 : out = 8'b00100000; - 3'b110 : out = 8'b01000000; - 3'b111 : out = 8'b10000000; - endcase -endmodule diff --git a/tests/hana/test_simulation_decoder_6_test.v b/tests/hana/test_simulation_decoder_6_test.v deleted file mode 100644 index fd19ad609..000000000 --- a/tests/hana/test_simulation_decoder_6_test.v +++ /dev/null @@ -1,27 +0,0 @@ -module test (input [3:0] in, input enable, output reg [15:0] out); - -always @(in or enable) - if(!enable) - out = 16'b0000000000000000; - else begin - case (in) - 4'b0000 : out = 16'b0000000000000001; - 4'b0001 : out = 16'b0000000000000010; - 4'b0010 : out = 16'b0000000000000100; - 4'b0011 : out = 16'b0000000000001000; - 4'b0100 : out = 16'b0000000000010000; - 4'b0101 : out = 16'b0000000000100000; - 4'b0110 : out = 16'b0000000001000000; - 4'b0111 : out = 16'b0000000010000000; - 4'b1000 : out = 16'b0000000100000000; - 4'b1001 : out = 16'b0000001000000000; - 4'b1010 : out = 16'b0000010000000000; - 4'b1011 : out = 16'b0000100000000000; - 4'b1100 : out = 16'b0001000000000000; - 4'b1101 : out = 16'b0010000000000000; - 4'b1110 : out = 16'b0100000000000000; - 4'b1111 : out = 16'b1000000000000000; - endcase - end -endmodule - diff --git a/tests/hana/test_simulation_decoder_7_test.v b/tests/hana/test_simulation_decoder_7_test.v deleted file mode 100644 index 462e94199..000000000 --- a/tests/hana/test_simulation_decoder_7_test.v +++ /dev/null @@ -1,43 +0,0 @@ -module test (input [4:0] in, input enable, output reg [31:0] out); - -always @(in or enable) - if(!enable) - out = 32'b00000000000000000000000000000000; - else begin - case (in) - 5'b00000 : out = 32'b00000000000000000000000000000001; - 5'b00001 : out = 32'b00000000000000000000000000000010; - 5'b00010 : out = 32'b00000000000000000000000000000100; - 5'b00011 : out = 32'b00000000000000000000000000001000; - 5'b00100 : out = 32'b00000000000000000000000000010000; - 5'b00101 : out = 32'b00000000000000000000000000100000; - 5'b00110 : out = 32'b00000000000000000000000001000000; - 5'b00111 : out = 32'b00000000000000000000000010000000; - 5'b01000 : out = 32'b00000000000000000000000100000000; - 5'b01001 : out = 32'b00000000000000000000001000000000; - 5'b01010 : out = 32'b00000000000000000000010000000000; - 5'b01011 : out = 32'b00000000000000000000100000000000; - 5'b01100 : out = 32'b00000000000000000001000000000000; - 5'b01101 : out = 32'b00000000000000000010000000000000; - 5'b01110 : out = 32'b00000000000000000100000000000000; - 5'b01111 : out = 32'b00000000000000001000000000000000; - 5'b10000 : out = 32'b00000000000000010000000000000000; - 5'b10001 : out = 32'b00000000000000100000000000000000; - 5'b10010 : out = 32'b00000000000001000000000000000000; - 5'b10011 : out = 32'b00000000000010000000000000000000; - 5'b10100 : out = 32'b00000000000100000000000000000000; - 5'b10101 : out = 32'b00000000001000000000000000000000; - 5'b10110 : out = 32'b00000000010000000000000000000000; - 5'b10111 : out = 32'b00000000100000000000000000000000; - 5'b11000 : out = 32'b00000001000000000000000000000000; - 5'b11001 : out = 32'b00000010000000000000000000000000; - 5'b11010 : out = 32'b00000100000000000000000000000000; - 5'b11011 : out = 32'b00001000000000000000000000000000; - 5'b11100 : out = 32'b00010000000000000000000000000000; - 5'b11101 : out = 32'b00100000000000000000000000000000; - 5'b11110 : out = 32'b01000000000000000000000000000000; - 5'b11111 : out = 32'b10000000000000000000000000000000; - endcase - end -endmodule - diff --git a/tests/hana/test_simulation_inc.v b/tests/hana/test_simulation_inc.v new file mode 100644 index 000000000..f8f548705 --- /dev/null +++ b/tests/hana/test_simulation_inc.v @@ -0,0 +1,42 @@ + +// test_simulation_inc_16_test.v +module f1_test(input [15:0] in, output [15:0] out); + +assign out = -in; + +endmodule + +// test_simulation_inc_1_test.v +module f2_test(input in, output out); + +assign out = -in; + +endmodule + +// test_simulation_inc_2_test.v +module f3_test(input [1:0] in, output [1:0] out); + +assign out = -in; + +endmodule + +// test_simulation_inc_32_test.v +module f4_test(input [31:0] in, output [31:0] out); + +assign out = -in; + +endmodule + +// test_simulation_inc_4_test.v +module f5_test(input [3:0] in, output [3:0] out); + +assign out = -in; + +endmodule + +// test_simulation_inc_8_test.v +module f6_test(input [7:0] in, output [7:0] out); + +assign out = -in; + +endmodule diff --git a/tests/hana/test_simulation_inc_16_test.v b/tests/hana/test_simulation_inc_16_test.v deleted file mode 100644 index 7ff42ff50..000000000 --- a/tests/hana/test_simulation_inc_16_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input [15:0] in, output [15:0] out); - -assign out = -in; - -endmodule diff --git a/tests/hana/test_simulation_inc_1_test.v b/tests/hana/test_simulation_inc_1_test.v deleted file mode 100644 index 02bec2c27..000000000 --- a/tests/hana/test_simulation_inc_1_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input in, output out); - -assign out = -in; - -endmodule diff --git a/tests/hana/test_simulation_inc_2_test.v b/tests/hana/test_simulation_inc_2_test.v deleted file mode 100644 index b96e05a2d..000000000 --- a/tests/hana/test_simulation_inc_2_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input [1:0] in, output [1:0] out); - -assign out = -in; - -endmodule diff --git a/tests/hana/test_simulation_inc_32_test.v b/tests/hana/test_simulation_inc_32_test.v deleted file mode 100644 index 5700d0ce7..000000000 --- a/tests/hana/test_simulation_inc_32_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input [31:0] in, output [31:0] out); - -assign out = -in; - -endmodule diff --git a/tests/hana/test_simulation_inc_4_test.v b/tests/hana/test_simulation_inc_4_test.v deleted file mode 100644 index 34940d63e..000000000 --- a/tests/hana/test_simulation_inc_4_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input [3:0] in, output [3:0] out); - -assign out = -in; - -endmodule diff --git a/tests/hana/test_simulation_inc_8_test.v b/tests/hana/test_simulation_inc_8_test.v deleted file mode 100644 index c36d69f07..000000000 --- a/tests/hana/test_simulation_inc_8_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input [7:0] in, output [7:0] out); - -assign out = -in; - -endmodule diff --git a/tests/hana/test_simulation_mod_1_xx.v b/tests/hana/test_simulation_mod_1_xx.v deleted file mode 100644 index 75144a8e5..000000000 --- a/tests/hana/test_simulation_mod_1_xx.v +++ /dev/null @@ -1,13 +0,0 @@ -module test(in1, in2, out); -input in1; -input in2; -output out; - -wire synth_net_0; -wire synth_net_1; -BUF synth_BUF_0(.in(synth_net_1), .out(out - )); -DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1 - )); -endmodule - diff --git a/tests/hana/test_simulation_mux.v b/tests/hana/test_simulation_mux.v new file mode 100644 index 000000000..085387eff --- /dev/null +++ b/tests/hana/test_simulation_mux.v @@ -0,0 +1,176 @@ + +// test_simulation_mux_16_test.v +module f1_test(input [15:0] in, input [3:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + 4: out = in[4]; + 5: out = in[5]; + 6: out = in[6]; + 7: out = in[7]; + 8: out = in[8]; + 9: out = in[9]; + 10: out = in[10]; + 11: out = in[11]; + 12: out = in[12]; + 13: out = in[13]; + 14: out = in[14]; + 15: out = in[15]; + endcase +endmodule + +// test_simulation_mux_2_test.v +module f2_test(input [1:0] in, input select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + endcase +endmodule + +// test_simulation_mux_32_test.v +module f3_test(input [31:0] in, input [4:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + 4: out = in[4]; + 5: out = in[5]; + 6: out = in[6]; + 7: out = in[7]; + 8: out = in[8]; + 9: out = in[9]; + 10: out = in[10]; + 11: out = in[11]; + 12: out = in[12]; + 13: out = in[13]; + 14: out = in[14]; + 15: out = in[15]; + 16: out = in[16]; + 17: out = in[17]; + 18: out = in[18]; + 19: out = in[19]; + 20: out = in[20]; + 21: out = in[21]; + 22: out = in[22]; + 23: out = in[23]; + 24: out = in[24]; + 25: out = in[25]; + 26: out = in[26]; + 27: out = in[27]; + 28: out = in[28]; + 29: out = in[29]; + 30: out = in[30]; + 31: out = in[31]; + endcase +endmodule + + +// test_simulation_mux_4_test.v +module f4_test(input [3:0] in, input [1:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + endcase +endmodule + +// test_simulation_mux_64_test.v +module f5_test(input [63:0] in, input [5:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + 4: out = in[4]; + 5: out = in[5]; + 6: out = in[6]; + 7: out = in[7]; + 8: out = in[8]; + 9: out = in[9]; + 10: out = in[10]; + 11: out = in[11]; + 12: out = in[12]; + 13: out = in[13]; + 14: out = in[14]; + 15: out = in[15]; + 16: out = in[16]; + 17: out = in[17]; + 18: out = in[18]; + 19: out = in[19]; + 20: out = in[20]; + 21: out = in[21]; + 22: out = in[22]; + 23: out = in[23]; + 24: out = in[24]; + 25: out = in[25]; + 26: out = in[26]; + 27: out = in[27]; + 28: out = in[28]; + 29: out = in[29]; + 30: out = in[30]; + 31: out = in[31]; + 32: out = in[32]; + 33: out = in[33]; + 34: out = in[34]; + 35: out = in[35]; + 36: out = in[36]; + 37: out = in[37]; + 38: out = in[38]; + 39: out = in[39]; + 40: out = in[40]; + 41: out = in[41]; + 42: out = in[42]; + 43: out = in[43]; + 44: out = in[44]; + 45: out = in[45]; + 46: out = in[46]; + 47: out = in[47]; + 48: out = in[48]; + 49: out = in[49]; + 50: out = in[50]; + 51: out = in[51]; + 52: out = in[52]; + 53: out = in[53]; + 54: out = in[54]; + 55: out = in[55]; + 56: out = in[56]; + 57: out = in[57]; + 58: out = in[58]; + 59: out = in[59]; + 60: out = in[60]; + 61: out = in[61]; + 62: out = in[62]; + 63: out = in[63]; + endcase +endmodule + + +// test_simulation_mux_8_test.v +module f6_test(input [7:0] in, input [2:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + 4: out = in[4]; + 5: out = in[5]; + 6: out = in[6]; + 7: out = in[7]; + endcase +endmodule diff --git a/tests/hana/test_simulation_mux_16_test.v b/tests/hana/test_simulation_mux_16_test.v deleted file mode 100644 index de4b6f8e9..000000000 --- a/tests/hana/test_simulation_mux_16_test.v +++ /dev/null @@ -1,22 +0,0 @@ -module test(input [15:0] in, input [3:0] select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - 2: out = in[2]; - 3: out = in[3]; - 4: out = in[4]; - 5: out = in[5]; - 6: out = in[6]; - 7: out = in[7]; - 8: out = in[8]; - 9: out = in[9]; - 10: out = in[10]; - 11: out = in[11]; - 12: out = in[12]; - 13: out = in[13]; - 14: out = in[14]; - 15: out = in[15]; - endcase -endmodule diff --git a/tests/hana/test_simulation_mux_2_test.v b/tests/hana/test_simulation_mux_2_test.v deleted file mode 100644 index bc676c70b..000000000 --- a/tests/hana/test_simulation_mux_2_test.v +++ /dev/null @@ -1,8 +0,0 @@ -module test(input [1:0] in, input select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - endcase -endmodule diff --git a/tests/hana/test_simulation_mux_32_test.v b/tests/hana/test_simulation_mux_32_test.v deleted file mode 100644 index 16de4d7f7..000000000 --- a/tests/hana/test_simulation_mux_32_test.v +++ /dev/null @@ -1,39 +0,0 @@ -module test(input [31:0] in, input [4:0] select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - 2: out = in[2]; - 3: out = in[3]; - 4: out = in[4]; - 5: out = in[5]; - 6: out = in[6]; - 7: out = in[7]; - 8: out = in[8]; - 9: out = in[9]; - 10: out = in[10]; - 11: out = in[11]; - 12: out = in[12]; - 13: out = in[13]; - 14: out = in[14]; - 15: out = in[15]; - 16: out = in[16]; - 17: out = in[17]; - 18: out = in[18]; - 19: out = in[19]; - 20: out = in[20]; - 21: out = in[21]; - 22: out = in[22]; - 23: out = in[23]; - 24: out = in[24]; - 25: out = in[25]; - 26: out = in[26]; - 27: out = in[27]; - 28: out = in[28]; - 29: out = in[29]; - 30: out = in[30]; - 31: out = in[31]; - endcase -endmodule - diff --git a/tests/hana/test_simulation_mux_4_test.v b/tests/hana/test_simulation_mux_4_test.v deleted file mode 100644 index 6a112c6a9..000000000 --- a/tests/hana/test_simulation_mux_4_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test(input [3:0] in, input [1:0] select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - 2: out = in[2]; - 3: out = in[3]; - endcase -endmodule diff --git a/tests/hana/test_simulation_mux_64_test.v b/tests/hana/test_simulation_mux_64_test.v deleted file mode 100644 index 420239c6e..000000000 --- a/tests/hana/test_simulation_mux_64_test.v +++ /dev/null @@ -1,71 +0,0 @@ -module test(input [63:0] in, input [5:0] select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - 2: out = in[2]; - 3: out = in[3]; - 4: out = in[4]; - 5: out = in[5]; - 6: out = in[6]; - 7: out = in[7]; - 8: out = in[8]; - 9: out = in[9]; - 10: out = in[10]; - 11: out = in[11]; - 12: out = in[12]; - 13: out = in[13]; - 14: out = in[14]; - 15: out = in[15]; - 16: out = in[16]; - 17: out = in[17]; - 18: out = in[18]; - 19: out = in[19]; - 20: out = in[20]; - 21: out = in[21]; - 22: out = in[22]; - 23: out = in[23]; - 24: out = in[24]; - 25: out = in[25]; - 26: out = in[26]; - 27: out = in[27]; - 28: out = in[28]; - 29: out = in[29]; - 30: out = in[30]; - 31: out = in[31]; - 32: out = in[32]; - 33: out = in[33]; - 34: out = in[34]; - 35: out = in[35]; - 36: out = in[36]; - 37: out = in[37]; - 38: out = in[38]; - 39: out = in[39]; - 40: out = in[40]; - 41: out = in[41]; - 42: out = in[42]; - 43: out = in[43]; - 44: out = in[44]; - 45: out = in[45]; - 46: out = in[46]; - 47: out = in[47]; - 48: out = in[48]; - 49: out = in[49]; - 50: out = in[50]; - 51: out = in[51]; - 52: out = in[52]; - 53: out = in[53]; - 54: out = in[54]; - 55: out = in[55]; - 56: out = in[56]; - 57: out = in[57]; - 58: out = in[58]; - 59: out = in[59]; - 60: out = in[60]; - 61: out = in[61]; - 62: out = in[62]; - 63: out = in[63]; - endcase -endmodule - diff --git a/tests/hana/test_simulation_mux_8_test.v b/tests/hana/test_simulation_mux_8_test.v deleted file mode 100644 index f53a2c570..000000000 --- a/tests/hana/test_simulation_mux_8_test.v +++ /dev/null @@ -1,14 +0,0 @@ -module test(input [7:0] in, input [2:0] select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - 2: out = in[2]; - 3: out = in[3]; - 4: out = in[4]; - 5: out = in[5]; - 6: out = in[6]; - 7: out = in[7]; - endcase -endmodule diff --git a/tests/hana/test_simulation_nand.v b/tests/hana/test_simulation_nand.v new file mode 100644 index 000000000..5e6e0f1f5 --- /dev/null +++ b/tests/hana/test_simulation_nand.v @@ -0,0 +1,25 @@ + +// test_simulation_nand_1_test.v +module f1_test(input [1:0] in, output out); +assign out = ~(in[0] & in[1]); +endmodule + +// test_simulation_nand_3_test.v +module f2_test(input [2:0] in, output out); +assign out = !(in[0] & in[1] & in[2]); +endmodule + +// test_simulation_nand_4_test.v +module f3_test(input [2:0] in, output out); +assign out = ~(in[0] && in[1] && in[2]); +endmodule + +// test_simulation_nand_5_test.v +module f4_test(input [3:0] in, output out); +assign out = !(in[0] & in[1] & in[2] & in[3]); +endmodule + +// test_simulation_nand_6_test.v +module f5_test(input [3:0] in, output out); +assign out = !(in[0] && in[1] && in[2] && in[3]); +endmodule diff --git a/tests/hana/test_simulation_nand_1_test.v b/tests/hana/test_simulation_nand_1_test.v deleted file mode 100644 index d8f34ee1f..000000000 --- a/tests/hana/test_simulation_nand_1_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, output out); -assign out = ~(in[0] & in[1]); -endmodule diff --git a/tests/hana/test_simulation_nand_3_test.v b/tests/hana/test_simulation_nand_3_test.v deleted file mode 100644 index 8926cebb9..000000000 --- a/tests/hana/test_simulation_nand_3_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = !(in[0] & in[1] & in[2]); -endmodule diff --git a/tests/hana/test_simulation_nand_4_test.v b/tests/hana/test_simulation_nand_4_test.v deleted file mode 100644 index 703a2de45..000000000 --- a/tests/hana/test_simulation_nand_4_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = ~(in[0] && in[1] && in[2]); -endmodule diff --git a/tests/hana/test_simulation_nand_5_test.v b/tests/hana/test_simulation_nand_5_test.v deleted file mode 100644 index adef3c903..000000000 --- a/tests/hana/test_simulation_nand_5_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = !(in[0] & in[1] & in[2] & in[3]); -endmodule diff --git a/tests/hana/test_simulation_nand_6_test.v b/tests/hana/test_simulation_nand_6_test.v deleted file mode 100644 index a2136f211..000000000 --- a/tests/hana/test_simulation_nand_6_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = !(in[0] && in[1] && in[2] && in[3]); -endmodule diff --git a/tests/hana/test_simulation_nor.v b/tests/hana/test_simulation_nor.v new file mode 100644 index 000000000..d7d2bc0ec --- /dev/null +++ b/tests/hana/test_simulation_nor.v @@ -0,0 +1,20 @@ + +// test_simulation_nor_1_test.v +module f1_test(input [1:0] in, output out); +assign out = ~(in[0] | in[1]); +endmodule + +// test_simulation_nor_2_test.v +module f2_test(input [2:0] in, output out); +assign out = ~(in[0] | in[1] | in[2]); +endmodule + +// test_simulation_nor_3_test.v +module f3_test(input [3:0] in, output out); +assign out = ~(in[0] | in[1] | in[2] | in[3]); +endmodule + +// test_simulation_nor_4_test.v +module f4_test(input [3:0] in, output out); +nor mynor(out, in[0], in[1], in[2], in[3]); +endmodule diff --git a/tests/hana/test_simulation_nor_1_test.v b/tests/hana/test_simulation_nor_1_test.v deleted file mode 100644 index df4e8bfaa..000000000 --- a/tests/hana/test_simulation_nor_1_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, output out); -assign out = ~(in[0] | in[1]); -endmodule diff --git a/tests/hana/test_simulation_nor_2_test.v b/tests/hana/test_simulation_nor_2_test.v deleted file mode 100644 index 2cfffc45f..000000000 --- a/tests/hana/test_simulation_nor_2_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = ~(in[0] | in[1] | in[2]); -endmodule diff --git a/tests/hana/test_simulation_nor_3_test.v b/tests/hana/test_simulation_nor_3_test.v deleted file mode 100644 index 9f1ef8fec..000000000 --- a/tests/hana/test_simulation_nor_3_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = ~(in[0] | in[1] | in[2] | in[3]); -endmodule diff --git a/tests/hana/test_simulation_nor_4_test.v b/tests/hana/test_simulation_nor_4_test.v deleted file mode 100644 index d8e685049..000000000 --- a/tests/hana/test_simulation_nor_4_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -nor mynor(out, in[0], in[1], in[2], in[3]); -endmodule diff --git a/tests/hana/test_simulation_opt_constprop_contassign_1_test.v b/tests/hana/test_simulation_opt_constprop_contassign_1_test.v deleted file mode 100644 index a39b58b42..000000000 --- a/tests/hana/test_simulation_opt_constprop_contassign_1_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input in, output out); -assign out = 1'b1; -endmodule diff --git a/tests/hana/test_simulation_or.v b/tests/hana/test_simulation_or.v new file mode 100644 index 000000000..9217db808 --- /dev/null +++ b/tests/hana/test_simulation_or.v @@ -0,0 +1,30 @@ + +// test_simulation_or_1_test.v +module f1_test(input [1:0] in, output out); +assign out = in[0] | in[1]; +endmodule + +// test_simulation_or_2_test.v +module f2_test(input [1:0] in, output out); +assign out = in[0] || in[1]; +endmodule + +// test_simulation_or_3_test.v +module f3_test(input [2:0] in, output out); +assign out = in[0] | in[1] | in[2]; +endmodule + +// test_simulation_or_4_test.v +module f4_test(input [2:0] in, output out); +assign out = in[0] || in[1] || in[2]; +endmodule + +// test_simulation_or_5_test.v +module f5_test(input [3:0] in, output out); +assign out = in[0] | in[1] | in[2] | in[3]; +endmodule + +// test_simulation_or_6_test.v +module f6_test(input [3:0] in, output out); +assign out = in[0] || in[1] || in[2] || in[3]; +endmodule diff --git a/tests/hana/test_simulation_or_1_test.v b/tests/hana/test_simulation_or_1_test.v deleted file mode 100644 index bdfffd3d7..000000000 --- a/tests/hana/test_simulation_or_1_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, output out); -assign out = in[0] | in[1]; -endmodule diff --git a/tests/hana/test_simulation_or_2_test.v b/tests/hana/test_simulation_or_2_test.v deleted file mode 100644 index 291c8c765..000000000 --- a/tests/hana/test_simulation_or_2_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, output out); -assign out = in[0] || in[1]; -endmodule diff --git a/tests/hana/test_simulation_or_3_test.v b/tests/hana/test_simulation_or_3_test.v deleted file mode 100644 index ad00c7084..000000000 --- a/tests/hana/test_simulation_or_3_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = in[0] | in[1] | in[2]; -endmodule diff --git a/tests/hana/test_simulation_or_4_test.v b/tests/hana/test_simulation_or_4_test.v deleted file mode 100644 index 2ec57fa93..000000000 --- a/tests/hana/test_simulation_or_4_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = in[0] || in[1] || in[2]; -endmodule diff --git a/tests/hana/test_simulation_or_5_test.v b/tests/hana/test_simulation_or_5_test.v deleted file mode 100644 index f6a2d14d4..000000000 --- a/tests/hana/test_simulation_or_5_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = in[0] | in[1] | in[2] | in[3]; -endmodule diff --git a/tests/hana/test_simulation_or_6_test.v b/tests/hana/test_simulation_or_6_test.v deleted file mode 100644 index ecd85c363..000000000 --- a/tests/hana/test_simulation_or_6_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = in[0] || in[1] || in[2] || in[3]; -endmodule diff --git a/tests/hana/test_simulation_seq.v b/tests/hana/test_simulation_seq.v new file mode 100644 index 000000000..eba4e88ea --- /dev/null +++ b/tests/hana/test_simulation_seq.v @@ -0,0 +1,12 @@ + +// test_simulation_seq_ff_1_test.v +module f1_test(input in, input clk, output reg out); +always @(posedge clk) + out <= in; +endmodule + +// test_simulation_seq_ff_2_test.v +module f2_test(input in, input clk, output reg out); +always @(negedge clk) + out <= in; +endmodule diff --git a/tests/hana/test_simulation_seq_ff_1_test.v b/tests/hana/test_simulation_seq_ff_1_test.v deleted file mode 100644 index 5aac49c03..000000000 --- a/tests/hana/test_simulation_seq_ff_1_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input in, input clk, output reg out); -always @(posedge clk) - out <= in; -endmodule diff --git a/tests/hana/test_simulation_seq_ff_2_test.v b/tests/hana/test_simulation_seq_ff_2_test.v deleted file mode 100644 index f1d2b7b42..000000000 --- a/tests/hana/test_simulation_seq_ff_2_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input in, input clk, output reg out); -always @(negedge clk) - out <= in; -endmodule diff --git a/tests/hana/test_simulation_shifter.v b/tests/hana/test_simulation_shifter.v new file mode 100644 index 000000000..8864fb0e7 --- /dev/null +++ b/tests/hana/test_simulation_shifter.v @@ -0,0 +1,60 @@ + +// test_simulation_shifter_left_16_test.v +module f1_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT); + +assign OUT = IN << SHIFT; +endmodule + +// test_simulation_shifter_left_32_test.v +module f2_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT); + +assign OUT = IN << SHIFT; +endmodule + +// test_simulation_shifter_left_4_test.v +module f3_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT); + +assign OUT = IN << SHIFT; +endmodule + +// test_simulation_shifter_left_64_test.v +module f4_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT); + +assign OUT = IN << SHIFT; +endmodule + +// test_simulation_shifter_left_8_test.v +module f5_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT); + +assign OUT = IN << SHIFT; +endmodule + +// test_simulation_shifter_right_16_test.v +module f6_test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT); + +assign OUT = IN >> SHIFT; +endmodule + +// test_simulation_shifter_right_32_test.v +module f7_test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT); + +assign OUT = IN >> SHIFT; +endmodule + +// test_simulation_shifter_right_4_test.v +module f8_test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT); + +assign OUT = IN >> SHIFT; +endmodule + +// test_simulation_shifter_right_64_test.v +module f9_test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT); + +assign OUT = IN >> SHIFT; +endmodule + +// test_simulation_shifter_right_8_test.v +module f10_test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT); + +assign OUT = IN >> SHIFT; +endmodule diff --git a/tests/hana/test_simulation_shifter_left_16_test.v b/tests/hana/test_simulation_shifter_left_16_test.v deleted file mode 100644 index a57dac499..000000000 --- a/tests/hana/test_simulation_shifter_left_16_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT); - -assign OUT = IN << SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_left_32_test.v b/tests/hana/test_simulation_shifter_left_32_test.v deleted file mode 100644 index 672938ace..000000000 --- a/tests/hana/test_simulation_shifter_left_32_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT); - -assign OUT = IN << SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_left_4_test.v b/tests/hana/test_simulation_shifter_left_4_test.v deleted file mode 100644 index c525401f1..000000000 --- a/tests/hana/test_simulation_shifter_left_4_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT); - -assign OUT = IN << SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_left_64_test.v b/tests/hana/test_simulation_shifter_left_64_test.v deleted file mode 100644 index 276a7c5a8..000000000 --- a/tests/hana/test_simulation_shifter_left_64_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT); - -assign OUT = IN << SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_left_8_test.v b/tests/hana/test_simulation_shifter_left_8_test.v deleted file mode 100644 index c17277001..000000000 --- a/tests/hana/test_simulation_shifter_left_8_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT); - -assign OUT = IN << SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_right_16_test.v b/tests/hana/test_simulation_shifter_right_16_test.v deleted file mode 100644 index 6152adc06..000000000 --- a/tests/hana/test_simulation_shifter_right_16_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [15:0] IN, input [4:0] SHIFT, output [15:0] OUT); - -assign OUT = IN >> SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_right_32_test.v b/tests/hana/test_simulation_shifter_right_32_test.v deleted file mode 100644 index e910cdd6d..000000000 --- a/tests/hana/test_simulation_shifter_right_32_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [31:0] IN, input [5:0] SHIFT, output [31:0] OUT); - -assign OUT = IN >> SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_right_4_test.v b/tests/hana/test_simulation_shifter_right_4_test.v deleted file mode 100644 index 608c196de..000000000 --- a/tests/hana/test_simulation_shifter_right_4_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [3:0] IN, input [2:0] SHIFT, output [3:0] OUT); - -assign OUT = IN >> SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_right_64_test.v b/tests/hana/test_simulation_shifter_right_64_test.v deleted file mode 100644 index c26d5938e..000000000 --- a/tests/hana/test_simulation_shifter_right_64_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [63:0] IN, input [6:0] SHIFT, output [63:0] OUT); - -assign OUT = IN >> SHIFT; -endmodule diff --git a/tests/hana/test_simulation_shifter_right_8_test.v b/tests/hana/test_simulation_shifter_right_8_test.v deleted file mode 100644 index a91c594e5..000000000 --- a/tests/hana/test_simulation_shifter_right_8_test.v +++ /dev/null @@ -1,4 +0,0 @@ -module test(input [7:0] IN, input [3:0] SHIFT, output [7:0] OUT); - -assign OUT = IN >> SHIFT; -endmodule diff --git a/tests/hana/test_simulation_sop.v b/tests/hana/test_simulation_sop.v new file mode 100644 index 000000000..79870cf0c --- /dev/null +++ b/tests/hana/test_simulation_sop.v @@ -0,0 +1,65 @@ + +// test_simulation_sop_basic_10_test.v +module f1_test(input [1:0] in, input select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + endcase +endmodule + +// test_simulation_sop_basic_11_test.v +module f2_test(input [3:0] in, input [1:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + endcase +endmodule + +// test_simulation_sop_basic_12_test.v +module f3_test(input [7:0] in, input [2:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + 4: out = in[4]; + 5: out = in[5]; + 6: out = in[6]; + 7: out = in[7]; + endcase +endmodule + +// test_simulation_sop_basic_18_test.v +module f4_test(input [7:0] in, output out); + +assign out = ~^in; + +endmodule + +// test_simulation_sop_basic_3_test.v +module f5_test(input in, output out); +assign out = ~in; +endmodule + +// test_simulation_sop_basic_7_test.v +module f6_test(input in, output out); +assign out = in; +endmodule + +// test_simulation_sop_basic_8_test.v +module f7_test(output out); +assign out = 1'b0; +endmodule + +// test_simulation_sop_basic_9_test.v +module f8_test(input in, output out); +assign out = ~in; +endmodule diff --git a/tests/hana/test_simulation_sop_basic_10_test.v b/tests/hana/test_simulation_sop_basic_10_test.v deleted file mode 100644 index bc676c70b..000000000 --- a/tests/hana/test_simulation_sop_basic_10_test.v +++ /dev/null @@ -1,8 +0,0 @@ -module test(input [1:0] in, input select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - endcase -endmodule diff --git a/tests/hana/test_simulation_sop_basic_11_test.v b/tests/hana/test_simulation_sop_basic_11_test.v deleted file mode 100644 index 6a112c6a9..000000000 --- a/tests/hana/test_simulation_sop_basic_11_test.v +++ /dev/null @@ -1,10 +0,0 @@ -module test(input [3:0] in, input [1:0] select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - 2: out = in[2]; - 3: out = in[3]; - endcase -endmodule diff --git a/tests/hana/test_simulation_sop_basic_12_test.v b/tests/hana/test_simulation_sop_basic_12_test.v deleted file mode 100644 index f53a2c570..000000000 --- a/tests/hana/test_simulation_sop_basic_12_test.v +++ /dev/null @@ -1,14 +0,0 @@ -module test(input [7:0] in, input [2:0] select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - 2: out = in[2]; - 3: out = in[3]; - 4: out = in[4]; - 5: out = in[5]; - 6: out = in[6]; - 7: out = in[7]; - endcase -endmodule diff --git a/tests/hana/test_simulation_sop_basic_18_test.v b/tests/hana/test_simulation_sop_basic_18_test.v deleted file mode 100644 index 03fc35b32..000000000 --- a/tests/hana/test_simulation_sop_basic_18_test.v +++ /dev/null @@ -1,5 +0,0 @@ -module test(input [7:0] in, output out); - -assign out = ~^in; - -endmodule diff --git a/tests/hana/test_simulation_sop_basic_3_test.v b/tests/hana/test_simulation_sop_basic_3_test.v deleted file mode 100644 index 81759c25d..000000000 --- a/tests/hana/test_simulation_sop_basic_3_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input in, output out); -assign out = ~in; -endmodule diff --git a/tests/hana/test_simulation_sop_basic_7_test.v b/tests/hana/test_simulation_sop_basic_7_test.v deleted file mode 100644 index e9bb7f617..000000000 --- a/tests/hana/test_simulation_sop_basic_7_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input in, output out); -assign out = in; -endmodule diff --git a/tests/hana/test_simulation_sop_basic_8_test.v b/tests/hana/test_simulation_sop_basic_8_test.v deleted file mode 100644 index a51ead0b2..000000000 --- a/tests/hana/test_simulation_sop_basic_8_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(output out); -assign out = 1'b0; -endmodule diff --git a/tests/hana/test_simulation_sop_basic_9_test.v b/tests/hana/test_simulation_sop_basic_9_test.v deleted file mode 100644 index 81759c25d..000000000 --- a/tests/hana/test_simulation_sop_basic_9_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input in, output out); -assign out = ~in; -endmodule diff --git a/tests/hana/test_simulation_techmap_mux_128_test.v b/tests/hana/test_simulation_techmap.v index 544c016a8..88e24d0e7 100644 --- a/tests/hana/test_simulation_techmap_mux_128_test.v +++ b/tests/hana/test_simulation_techmap.v @@ -1,4 +1,26 @@ -module test(input [127:0] in, input [6:0] select, output reg out); + +// test_simulation_techmap_buf_test.v +module f1_test(input in, output out); +assign out = in; +endmodule + +// test_simulation_techmap_inv_test.v +module f2_test(input in, output out); +assign out = ~in; +endmodule + +// test_simulation_techmap_mux_0_test.v +module f3_test(input [1:0] in, input select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + endcase +endmodule + +// test_simulation_techmap_mux_128_test.v +module f4_test(input [127:0] in, input [6:0] select, output reg out); always @( in or select) case (select) @@ -132,3 +154,19 @@ always @( in or select) 127: out = in[127]; endcase endmodule + +// test_simulation_techmap_mux_8_test.v +module f5_test(input [7:0] in, input [2:0] select, output reg out); + +always @( in or select) + case (select) + 0: out = in[0]; + 1: out = in[1]; + 2: out = in[2]; + 3: out = in[3]; + 4: out = in[4]; + 5: out = in[5]; + 6: out = in[6]; + 7: out = in[7]; + endcase +endmodule diff --git a/tests/hana/test_simulation_techmap_and_19_tech.v b/tests/hana/test_simulation_techmap_and_19_tech.v deleted file mode 100644 index 2491087cd..000000000 --- a/tests/hana/test_simulation_techmap_and_19_tech.v +++ /dev/null @@ -1,7 +0,0 @@ -module TECH_AND18(input [17:0] in, output out); -assign out = ∈ -endmodule - -module TECH_AND4(input [3:0] in, output out); -assign out = ∈ -endmodule diff --git a/tests/hana/test_simulation_techmap_and_5_tech.v b/tests/hana/test_simulation_techmap_and_5_tech.v deleted file mode 100644 index 6ec6a61c4..000000000 --- a/tests/hana/test_simulation_techmap_and_5_tech.v +++ /dev/null @@ -1,3 +0,0 @@ -module TECH_AND5(input [4:0] in, output out); -assign out = ∈ -endmodule diff --git a/tests/hana/test_simulation_techmap_buf_test.v b/tests/hana/test_simulation_techmap_buf_test.v deleted file mode 100644 index e9bb7f617..000000000 --- a/tests/hana/test_simulation_techmap_buf_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input in, output out); -assign out = in; -endmodule diff --git a/tests/hana/test_simulation_techmap_inv_test.v b/tests/hana/test_simulation_techmap_inv_test.v deleted file mode 100644 index 81759c25d..000000000 --- a/tests/hana/test_simulation_techmap_inv_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input in, output out); -assign out = ~in; -endmodule diff --git a/tests/hana/test_simulation_techmap_mux_0_test.v b/tests/hana/test_simulation_techmap_mux_0_test.v deleted file mode 100644 index bc676c70b..000000000 --- a/tests/hana/test_simulation_techmap_mux_0_test.v +++ /dev/null @@ -1,8 +0,0 @@ -module test(input [1:0] in, input select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - endcase -endmodule diff --git a/tests/hana/test_simulation_techmap_mux_8_test.v b/tests/hana/test_simulation_techmap_mux_8_test.v deleted file mode 100644 index f53a2c570..000000000 --- a/tests/hana/test_simulation_techmap_mux_8_test.v +++ /dev/null @@ -1,14 +0,0 @@ -module test(input [7:0] in, input [2:0] select, output reg out); - -always @( in or select) - case (select) - 0: out = in[0]; - 1: out = in[1]; - 2: out = in[2]; - 3: out = in[3]; - 4: out = in[4]; - 5: out = in[5]; - 6: out = in[6]; - 7: out = in[7]; - endcase -endmodule diff --git a/tests/hana/test_simulation_techmap_nand_19_tech.v b/tests/hana/test_simulation_techmap_nand_19_tech.v deleted file mode 100644 index 6a119e1ee..000000000 --- a/tests/hana/test_simulation_techmap_nand_19_tech.v +++ /dev/null @@ -1,11 +0,0 @@ -module TECH_NAND18(input [17:0] in, output out); -assign out = ~(&in); -endmodule - -module TECH_NAND4(input [3:0] in, output out); -assign out = ~(&in); -endmodule - -module TECH_NAND2(input [1:0] in, output out); -assign out = ~(&in); -endmodule diff --git a/tests/hana/test_simulation_techmap_nand_2_tech.v b/tests/hana/test_simulation_techmap_nand_2_tech.v deleted file mode 100644 index 6a119e1ee..000000000 --- a/tests/hana/test_simulation_techmap_nand_2_tech.v +++ /dev/null @@ -1,11 +0,0 @@ -module TECH_NAND18(input [17:0] in, output out); -assign out = ~(&in); -endmodule - -module TECH_NAND4(input [3:0] in, output out); -assign out = ~(&in); -endmodule - -module TECH_NAND2(input [1:0] in, output out); -assign out = ~(&in); -endmodule diff --git a/tests/hana/test_simulation_techmap_nand_5_tech.v b/tests/hana/test_simulation_techmap_nand_5_tech.v deleted file mode 100644 index 6a119e1ee..000000000 --- a/tests/hana/test_simulation_techmap_nand_5_tech.v +++ /dev/null @@ -1,11 +0,0 @@ -module TECH_NAND18(input [17:0] in, output out); -assign out = ~(&in); -endmodule - -module TECH_NAND4(input [3:0] in, output out); -assign out = ~(&in); -endmodule - -module TECH_NAND2(input [1:0] in, output out); -assign out = ~(&in); -endmodule diff --git a/tests/hana/test_simulation_techmap_nor_19_tech.v b/tests/hana/test_simulation_techmap_nor_19_tech.v deleted file mode 100644 index 89fb2c7e8..000000000 --- a/tests/hana/test_simulation_techmap_nor_19_tech.v +++ /dev/null @@ -1,11 +0,0 @@ -module TECH_NOR18(input [17:0] in, output out); -assign out = ~(|in); -endmodule - -module TECH_NOR4(input [3:0] in, output out); -assign out = ~(|in); -endmodule - -module TECH_NOR2(input [1:0] in, output out); -assign out = ~(|in); -endmodule diff --git a/tests/hana/test_simulation_techmap_nor_2_tech.v b/tests/hana/test_simulation_techmap_nor_2_tech.v deleted file mode 100644 index 89fb2c7e8..000000000 --- a/tests/hana/test_simulation_techmap_nor_2_tech.v +++ /dev/null @@ -1,11 +0,0 @@ -module TECH_NOR18(input [17:0] in, output out); -assign out = ~(|in); -endmodule - -module TECH_NOR4(input [3:0] in, output out); -assign out = ~(|in); -endmodule - -module TECH_NOR2(input [1:0] in, output out); -assign out = ~(|in); -endmodule diff --git a/tests/hana/test_simulation_techmap_nor_5_tech.v b/tests/hana/test_simulation_techmap_nor_5_tech.v deleted file mode 100644 index 89fb2c7e8..000000000 --- a/tests/hana/test_simulation_techmap_nor_5_tech.v +++ /dev/null @@ -1,11 +0,0 @@ -module TECH_NOR18(input [17:0] in, output out); -assign out = ~(|in); -endmodule - -module TECH_NOR4(input [3:0] in, output out); -assign out = ~(|in); -endmodule - -module TECH_NOR2(input [1:0] in, output out); -assign out = ~(|in); -endmodule diff --git a/tests/hana/test_simulation_techmap_or_19_tech.v b/tests/hana/test_simulation_techmap_or_19_tech.v deleted file mode 100644 index 745d7b71c..000000000 --- a/tests/hana/test_simulation_techmap_or_19_tech.v +++ /dev/null @@ -1,7 +0,0 @@ -module TECH_OR18(input [17:0] in, output out); -assign out = |in; -endmodule - -module TECH_OR4(input [3:0] in, output out); -assign out = |in; -endmodule diff --git a/tests/hana/test_simulation_techmap_or_5_tech.v b/tests/hana/test_simulation_techmap_or_5_tech.v deleted file mode 100644 index 05c38b670..000000000 --- a/tests/hana/test_simulation_techmap_or_5_tech.v +++ /dev/null @@ -1,3 +0,0 @@ -module TECH_OR5(input [4:0] in, output out); -assign out = |in; -endmodule diff --git a/tests/hana/test_simulation_techmap_tech.v b/tests/hana/test_simulation_techmap_tech.v new file mode 100644 index 000000000..60aeca5c1 --- /dev/null +++ b/tests/hana/test_simulation_techmap_tech.v @@ -0,0 +1,143 @@ + +// test_simulation_techmap_and_19_tech.v +module f1_TECH_AND18(input [17:0] in, output out); +assign out = ∈ +endmodule + +module f1_TECH_AND4(input [3:0] in, output out); +assign out = ∈ +endmodule + +// test_simulation_techmap_and_5_tech.v +module f2_TECH_AND5(input [4:0] in, output out); +assign out = ∈ +endmodule + +// test_simulation_techmap_nand_19_tech.v +module f3_TECH_NAND18(input [17:0] in, output out); +assign out = ~(&in); +endmodule + +module f3_TECH_NAND4(input [3:0] in, output out); +assign out = ~(&in); +endmodule + +module f3_TECH_NAND2(input [1:0] in, output out); +assign out = ~(&in); +endmodule + +// test_simulation_techmap_nand_2_tech.v +module f4_TECH_NAND18(input [17:0] in, output out); +assign out = ~(&in); +endmodule + +module f4_TECH_NAND4(input [3:0] in, output out); +assign out = ~(&in); +endmodule + +module f4_TECH_NAND2(input [1:0] in, output out); +assign out = ~(&in); +endmodule + +// test_simulation_techmap_nand_5_tech.v +module f5_TECH_NAND18(input [17:0] in, output out); +assign out = ~(&in); +endmodule + +module f5_TECH_NAND4(input [3:0] in, output out); +assign out = ~(&in); +endmodule + +module f5_TECH_NAND2(input [1:0] in, output out); +assign out = ~(&in); +endmodule + +// test_simulation_techmap_nor_19_tech.v +module f6_TECH_NOR18(input [17:0] in, output out); +assign out = ~(|in); +endmodule + +module f6_TECH_NOR4(input [3:0] in, output out); +assign out = ~(|in); +endmodule + +module f6_TECH_NOR2(input [1:0] in, output out); +assign out = ~(|in); +endmodule + +// test_simulation_techmap_nor_2_tech.v +module f7_TECH_NOR18(input [17:0] in, output out); +assign out = ~(|in); +endmodule + +module f7_TECH_NOR4(input [3:0] in, output out); +assign out = ~(|in); +endmodule + +module f7_TECH_NOR2(input [1:0] in, output out); +assign out = ~(|in); +endmodule + +// test_simulation_techmap_nor_5_tech.v +module f8_TECH_NOR18(input [17:0] in, output out); +assign out = ~(|in); +endmodule + +module f8_TECH_NOR4(input [3:0] in, output out); +assign out = ~(|in); +endmodule + +module f8_TECH_NOR2(input [1:0] in, output out); +assign out = ~(|in); +endmodule + +// test_simulation_techmap_or_19_tech.v +module f9_TECH_OR18(input [17:0] in, output out); +assign out = |in; +endmodule + +module f9_TECH_OR4(input [3:0] in, output out); +assign out = |in; +endmodule + +// test_simulation_techmap_or_5_tech.v +module f10_TECH_OR5(input [4:0] in, output out); +assign out = |in; +endmodule + +// test_simulation_techmap_xnor_2_tech.v +module f11_TECH_XOR5(input [4:0] in, output out); +assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4]; +endmodule +module f11_TECH_XOR2(input [1:0] in, output out); +assign out = in[0] ^ in[1]; +endmodule + +// test_simulation_techmap_xnor_5_tech.v +module f12_TECH_XOR5(input [4:0] in, output out); +assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4]; +endmodule +module f12_TECH_XOR2(input [1:0] in, output out); +assign out = in[0] ^ in[1]; +endmodule + +// test_simulation_techmap_xor_19_tech.v +module f13_TECH_XOR2(input [1:0] in, output out); +assign out = in[0] ^ in[1]; +endmodule + +// test_simulation_techmap_xor_2_tech.v +module f14_TECH_XOR5(input [4:0] in, output out); +assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4]; +endmodule +module f14_TECH_XOR2(input [1:0] in, output out); +assign out = in[0] ^ in[1]; +endmodule + +// test_simulation_techmap_xor_5_tech.v +module f15_TECH_XOR5(input [4:0] in, output out); +assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4]; +endmodule +module f15_TECH_XOR2(input [1:0] in, output out); +assign out = in[0] ^ in[1]; +endmodule diff --git a/tests/hana/test_simulation_techmap_xnor_2_tech.v b/tests/hana/test_simulation_techmap_xnor_2_tech.v deleted file mode 100644 index 4eb05683f..000000000 --- a/tests/hana/test_simulation_techmap_xnor_2_tech.v +++ /dev/null @@ -1,6 +0,0 @@ -module TECH_XOR5(input [4:0] in, output out); -assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4]; -endmodule -module TECH_XOR2(input [1:0] in, output out); -assign out = in[0] ^ in[1]; -endmodule diff --git a/tests/hana/test_simulation_techmap_xnor_5_tech.v b/tests/hana/test_simulation_techmap_xnor_5_tech.v deleted file mode 100644 index 4eb05683f..000000000 --- a/tests/hana/test_simulation_techmap_xnor_5_tech.v +++ /dev/null @@ -1,6 +0,0 @@ -module TECH_XOR5(input [4:0] in, output out); -assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4]; -endmodule -module TECH_XOR2(input [1:0] in, output out); -assign out = in[0] ^ in[1]; -endmodule diff --git a/tests/hana/test_simulation_techmap_xor_19_tech.v b/tests/hana/test_simulation_techmap_xor_19_tech.v deleted file mode 100644 index 2042a0ad0..000000000 --- a/tests/hana/test_simulation_techmap_xor_19_tech.v +++ /dev/null @@ -1,3 +0,0 @@ -module TECH_XOR2(input [1:0] in, output out); -assign out = in[0] ^ in[1]; -endmodule diff --git a/tests/hana/test_simulation_techmap_xor_2_tech.v b/tests/hana/test_simulation_techmap_xor_2_tech.v deleted file mode 100644 index 4eb05683f..000000000 --- a/tests/hana/test_simulation_techmap_xor_2_tech.v +++ /dev/null @@ -1,6 +0,0 @@ -module TECH_XOR5(input [4:0] in, output out); -assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4]; -endmodule -module TECH_XOR2(input [1:0] in, output out); -assign out = in[0] ^ in[1]; -endmodule diff --git a/tests/hana/test_simulation_techmap_xor_5_tech.v b/tests/hana/test_simulation_techmap_xor_5_tech.v deleted file mode 100644 index 4eb05683f..000000000 --- a/tests/hana/test_simulation_techmap_xor_5_tech.v +++ /dev/null @@ -1,6 +0,0 @@ -module TECH_XOR5(input [4:0] in, output out); -assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4]; -endmodule -module TECH_XOR2(input [1:0] in, output out); -assign out = in[0] ^ in[1]; -endmodule diff --git a/tests/hana/test_simulation_tribuf_2_test.v b/tests/hana/test_simulation_tribuf_2_test.v deleted file mode 100644 index 1e82aaf04..000000000 --- a/tests/hana/test_simulation_tribuf_2_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, input enable, output [1:0] out); -assign out = enable ? in : 2'bzz; -endmodule diff --git a/tests/hana/test_simulation_always_31_tt.v b/tests/hana/test_simulation_vlib.v index 299c0ca46..7d3af09c2 100644 --- a/tests/hana/test_simulation_always_31_tt.v +++ b/tests/hana/test_simulation_vlib.v @@ -1,4 +1,19 @@ -module test(clk, cond, data); +// test_simulation_mod_1_xx.v +module f1_test(in1, in2, out); +input in1; +input in2; +output out; + +wire synth_net_0; +wire synth_net_1; +BUF synth_BUF_0(.in(synth_net_1), .out(out + )); +DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1 + )); +endmodule + +// test_simulation_always_31_tt.v +module f2_test(clk, cond, data); input cond; input clk; output data; diff --git a/tests/hana/test_simulation_xnor.v b/tests/hana/test_simulation_xnor.v new file mode 100644 index 000000000..7286d1341 --- /dev/null +++ b/tests/hana/test_simulation_xnor.v @@ -0,0 +1,20 @@ + +// test_simulation_xnor_1_test.v +module f1_test(input [1:0] in, output out); +assign out = ~(in[0] ^ in[1]); +endmodule + +// test_simulation_xnor_2_test.v +module f2_test(input [2:0] in, output out); +assign out = ~(in[0] ^ in[1] ^ in[2]); +endmodule + +// test_simulation_xnor_3_test.v +module f3_test(input [3:0] in, output out); +assign out = ~(in[0] ^ in[1] ^ in[2] ^ in[3]); +endmodule + +// test_simulation_xnor_4_test.v +module f4_test(input [3:0] in, output out); +xnor myxnor(out, in[0], in[1], in[2], in[3]); +endmodule diff --git a/tests/hana/test_simulation_xnor_1_test.v b/tests/hana/test_simulation_xnor_1_test.v deleted file mode 100644 index adc6ae5ca..000000000 --- a/tests/hana/test_simulation_xnor_1_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, output out); -assign out = ~(in[0] ^ in[1]); -endmodule diff --git a/tests/hana/test_simulation_xnor_2_test.v b/tests/hana/test_simulation_xnor_2_test.v deleted file mode 100644 index 701bcc775..000000000 --- a/tests/hana/test_simulation_xnor_2_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = ~(in[0] ^ in[1] ^ in[2]); -endmodule diff --git a/tests/hana/test_simulation_xnor_3_test.v b/tests/hana/test_simulation_xnor_3_test.v deleted file mode 100644 index a8c87cc62..000000000 --- a/tests/hana/test_simulation_xnor_3_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = ~(in[0] ^ in[1] ^ in[2] ^ in[3]); -endmodule diff --git a/tests/hana/test_simulation_xnor_4_test.v b/tests/hana/test_simulation_xnor_4_test.v deleted file mode 100644 index fa671ff93..000000000 --- a/tests/hana/test_simulation_xnor_4_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -xnor myxnor(out, in[0], in[1], in[2], in[3]); -endmodule diff --git a/tests/hana/test_simulation_xor.v b/tests/hana/test_simulation_xor.v new file mode 100644 index 000000000..e181dd83a --- /dev/null +++ b/tests/hana/test_simulation_xor.v @@ -0,0 +1,20 @@ + +// test_simulation_xor_1_test.v +module f1_test(input [1:0] in, output out); +assign out = (in[0] ^ in[1]); +endmodule + +// test_simulation_xor_2_test.v +module f2_test(input [2:0] in, output out); +assign out = (in[0] ^ in[1] ^ in[2]); +endmodule + +// test_simulation_xor_3_test.v +module f3_test(input [3:0] in, output out); +assign out = (in[0] ^ in[1] ^ in[2] ^ in[3]); +endmodule + +// test_simulation_xor_4_test.v +module f4_test(input [3:0] in, output out); +xor myxor(out, in[0], in[1], in[2], in[3]); +endmodule diff --git a/tests/hana/test_simulation_xor_1_test.v b/tests/hana/test_simulation_xor_1_test.v deleted file mode 100644 index f6447f817..000000000 --- a/tests/hana/test_simulation_xor_1_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [1:0] in, output out); -assign out = (in[0] ^ in[1]); -endmodule diff --git a/tests/hana/test_simulation_xor_2_test.v b/tests/hana/test_simulation_xor_2_test.v deleted file mode 100644 index d94081df7..000000000 --- a/tests/hana/test_simulation_xor_2_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [2:0] in, output out); -assign out = (in[0] ^ in[1] ^ in[2]); -endmodule diff --git a/tests/hana/test_simulation_xor_3_test.v b/tests/hana/test_simulation_xor_3_test.v deleted file mode 100644 index cfa13187f..000000000 --- a/tests/hana/test_simulation_xor_3_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -assign out = (in[0] ^ in[1] ^ in[2] ^ in[3]); -endmodule diff --git a/tests/hana/test_simulation_xor_4_test.v b/tests/hana/test_simulation_xor_4_test.v deleted file mode 100644 index be6cab633..000000000 --- a/tests/hana/test_simulation_xor_4_test.v +++ /dev/null @@ -1,3 +0,0 @@ -module test(input [3:0] in, output out); -xor myxor(out, in[0], in[1], in[2], in[3]); -endmodule diff --git a/tests/memories/.gitignore b/tests/memories/.gitignore new file mode 100644 index 000000000..90a0983a6 --- /dev/null +++ b/tests/memories/.gitignore @@ -0,0 +1,3 @@ +*.log +*.out +*.dmp diff --git a/tests/memories/amber23_sram_byte_en.v b/tests/memories/amber23_sram_byte_en.v new file mode 100644 index 000000000..3554af887 --- /dev/null +++ b/tests/memories/amber23_sram_byte_en.v @@ -0,0 +1,84 @@ +////////////////////////////////////////////////////////////////// +// // +// Generic Library SRAM with per byte write enable // +// // +// This file is part of the Amber project // +// http://www.opencores.org/project,amber // +// // +// Description // +// Configurable depth and width. The DATA_WIDTH must be a // +// multiple of 8. // +// // +// Author(s): // +// - Conor Santifort, csantifort.amber@gmail.com // +// // +////////////////////////////////////////////////////////////////// +// // +// Copyright (C) 2010 Authors and OPENCORES.ORG // +// // +// This source file may be used and distributed without // +// restriction provided that this copyright statement is not // +// removed from the file and that any derivative work contains // +// the original copyright notice and the associated disclaimer. // +// // +// This source file is free software; you can redistribute it // +// and/or modify it under the terms of the GNU Lesser General // +// Public License as published by the Free Software Foundation; // +// either version 2.1 of the License, or (at your option) any // +// later version. // +// // +// This source is distributed in the hope that it will be // +// useful, but WITHOUT ANY WARRANTY; without even the implied // +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // +// PURPOSE. See the GNU Lesser General Public License for more // +// details. // +// // +// You should have received a copy of the GNU Lesser General // +// Public License along with this source; if not, download it // +// from http://www.opencores.org/lgpl.shtml // +// // +////////////////////////////////////////////////////////////////// + +// expect-wr-ports 1 +// expect-rd-ports 1 + +module generic_sram_byte_en +#( +parameter DATA_WIDTH = 32, +parameter ADDRESS_WIDTH = 4 +) + +( +input i_clk, +input [DATA_WIDTH-1:0] i_write_data, +input i_write_enable, +input [ADDRESS_WIDTH-1:0] i_address, +input [DATA_WIDTH/8-1:0] i_byte_enable, +output reg [DATA_WIDTH-1:0] o_read_data + ); + +reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1]; +integer i; + +always @(posedge i_clk) + begin + // read + o_read_data <= i_write_enable ? {DATA_WIDTH{1'd0}} : mem[i_address]; + + // write + if (i_write_enable) + for (i=0;i<DATA_WIDTH/8;i=i+1) + begin + mem[i_address][i*8+0] <= i_byte_enable[i] ? i_write_data[i*8+0] : mem[i_address][i*8+0] ; + mem[i_address][i*8+1] <= i_byte_enable[i] ? i_write_data[i*8+1] : mem[i_address][i*8+1] ; + mem[i_address][i*8+2] <= i_byte_enable[i] ? i_write_data[i*8+2] : mem[i_address][i*8+2] ; + mem[i_address][i*8+3] <= i_byte_enable[i] ? i_write_data[i*8+3] : mem[i_address][i*8+3] ; + mem[i_address][i*8+4] <= i_byte_enable[i] ? i_write_data[i*8+4] : mem[i_address][i*8+4] ; + mem[i_address][i*8+5] <= i_byte_enable[i] ? i_write_data[i*8+5] : mem[i_address][i*8+5] ; + mem[i_address][i*8+6] <= i_byte_enable[i] ? i_write_data[i*8+6] : mem[i_address][i*8+6] ; + mem[i_address][i*8+7] <= i_byte_enable[i] ? i_write_data[i*8+7] : mem[i_address][i*8+7] ; + end + end + +endmodule + diff --git a/tests/memories/implicit_en.v b/tests/memories/implicit_en.v new file mode 100644 index 000000000..cfce378b4 --- /dev/null +++ b/tests/memories/implicit_en.v @@ -0,0 +1,24 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 + +module test(clk, rd_addr, rd_data, wr_addr, wr_en, wr_data); + +input clk; + +input [3:0] rd_addr; +output reg [31:0] rd_data; + +input [3:0] wr_addr, wr_en; +input [31:0] wr_data; + +reg [31:0] mem [0:15]; + +always @(posedge clk) begin + mem[wr_addr][ 7: 0] <= wr_en[0] ? wr_data[ 7: 0] : mem[wr_addr][ 7: 0]; + mem[wr_addr][15: 8] <= wr_en[1] ? wr_data[15: 8] : mem[wr_addr][15: 8]; + mem[wr_addr][23:16] <= wr_en[2] ? wr_data[23:16] : mem[wr_addr][23:16]; + mem[wr_addr][31:24] <= wr_en[3] ? wr_data[31:24] : mem[wr_addr][31:24]; + rd_data <= mem[rd_addr]; +end + +endmodule diff --git a/tests/memories/no_implicit_en.v b/tests/memories/no_implicit_en.v new file mode 100644 index 000000000..0e96e4ae1 --- /dev/null +++ b/tests/memories/no_implicit_en.v @@ -0,0 +1,24 @@ +// expect-wr-ports 1 +// expect-rd-ports 2 + +module test(clk, rd_addr, rd_data, cp_addr, wr_addr, wr_en, wr_data); + +input clk; + +input [3:0] rd_addr; +output reg [31:0] rd_data; + +input [3:0] cp_addr, wr_addr, wr_en; +input [31:0] wr_data; + +reg [31:0] mem [0:15]; + +always @(posedge clk) begin + mem[wr_addr][ 7: 0] <= wr_en[0] ? wr_data[ 7: 0] : mem[cp_addr][ 7: 0]; + mem[wr_addr][15: 8] <= wr_en[1] ? wr_data[15: 8] : mem[cp_addr][15: 8]; + mem[wr_addr][23:16] <= wr_en[2] ? wr_data[23:16] : mem[cp_addr][23:16]; + mem[wr_addr][31:24] <= wr_en[3] ? wr_data[31:24] : mem[cp_addr][31:24]; + rd_data <= mem[rd_addr]; +end + +endmodule diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh new file mode 100755 index 000000000..c3b196188 --- /dev/null +++ b/tests/memories/run-test.sh @@ -0,0 +1,19 @@ +#!/bin/bash + +set -e +bash ../tools/autotest.sh -G *.v + +for f in `egrep -l 'expect-(wr|rd)-ports' *.v`; do + echo -n "Testing expectations for $f .." + ../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem" $f + if grep -q expect-wr-ports $f; then + grep -q "parameter \\\\WR_PORTS $(gawk '/expect-wr-ports/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected number of write ports."; false; } + fi + if grep -q expect-rd-ports $f; then + grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected number of read ports."; false; } + fi + echo " ok." +done + diff --git a/tests/memories/shared_ports.v b/tests/memories/shared_ports.v new file mode 100644 index 000000000..94bad53e2 --- /dev/null +++ b/tests/memories/shared_ports.v @@ -0,0 +1,25 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 + +module test( + input clk, + input wr_en1, wr_en2, wr_en3, + input [3:0] wr_addr1, wr_addr2, wr_addr3, + input [15:0] wr_data, + input [3:0] rd_addr, + output reg [31:0] rd_data +); + +reg [31:0] mem [0:15]; + +always @(posedge clk) begin + if (wr_en1) + mem[wr_addr1][15:0] <= wr_data; + else if (wr_en2) + mem[wr_addr2][23:8] <= wr_data; + else if (wr_en3) + mem[wr_addr3][31:16] <= wr_data; + rd_data <= mem[rd_addr]; +end + +endmodule diff --git a/tests/memories/simple_sram_byte_en.v b/tests/memories/simple_sram_byte_en.v new file mode 100644 index 000000000..dee1d228f --- /dev/null +++ b/tests/memories/simple_sram_byte_en.v @@ -0,0 +1,26 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 + +module generic_sram_byte_en #( + parameter DATA_WIDTH = 32, + parameter ADDRESS_WIDTH = 4 +) ( + input i_clk, + input [DATA_WIDTH-1:0] i_write_data, + input i_write_enable, + input [ADDRESS_WIDTH-1:0] i_address, + input [DATA_WIDTH/8-1:0] i_byte_enable, + output reg [DATA_WIDTH-1:0] o_read_data +); + +reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1]; +integer i; + +always @(posedge i_clk) begin + for (i=0;i<DATA_WIDTH/8;i=i+1) + if (i_write_enable && i_byte_enable[i]) + mem[i_address][i*8 +: 8] <= i_write_data[i*8 +: 8]; + o_read_data <= mem[i_address]; +end + +endmodule diff --git a/tests/realmath/.gitignore b/tests/realmath/.gitignore new file mode 100644 index 000000000..9c595a6fb --- /dev/null +++ b/tests/realmath/.gitignore @@ -0,0 +1 @@ +temp diff --git a/tests/realmath/generate.py b/tests/realmath/generate.py new file mode 100644 index 000000000..972021dc8 --- /dev/null +++ b/tests/realmath/generate.py @@ -0,0 +1,91 @@ +#!/usr/bin/python + +from __future__ import division +from __future__ import print_function + +import sys +import random +from contextlib import contextmanager + +@contextmanager +def redirect_stdout(new_target): + old_target, sys.stdout = sys.stdout, new_target + try: + yield new_target + finally: + sys.stdout = old_target + +def random_expression(depth = 3, maxparam = 0): + def recursion(): + return random_expression(depth = depth-1, maxparam = maxparam) + if depth == 0: + if maxparam != 0 and random.randint(0, 1) != 0: + return 'p%02d' % random.randint(0, maxparam-1) + return random.choice([ '%e', '%f', '%g' ]) % random.uniform(-2, +2) + if random.randint(0, 4) == 0: + return recursion() + random.choice([ ' < ', ' <= ', ' == ', ' != ', ' >= ', ' > ' ]) + recursion() + ' ? ' + recursion() + ' : ' + recursion() + op_prefix = [ '+(', '-(' ] + op_infix = [ ' + ', ' - ', ' * ', ' / ' ] + op_func1 = [ '$ln', '$log10', '$exp', '$sqrt', '$floor', '$ceil', '$sin', '$cos', '$tan', '$asin', '$acos', '$atan', '$sinh', '$cosh', '$tanh', '$asinh', '$acosh', '$atanh' ] + op_func2 = [ '$pow', '$atan2', '$hypot' ] + op = random.choice(op_prefix + op_infix + op_func1 + op_func2) + if op in op_prefix: + return op + recursion() + ')' + if op in op_infix: + return '(' + recursion() + op + recursion() + ')' + if op in op_func1: + return op + '(' + recursion() + ')' + if op in op_func2: + return op + '(' + recursion() + ', ' + recursion() + ')' + raise + +for idx in range(100): + with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): + print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)]))) + for i in range(30): + if idx < 10: + print('localparam p%02d = %s;' % (i, random_expression())) + else: + print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression())) + for i in range(30, 60): + if idx < 10: + print('localparam p%02d = %s;' % (i, random_expression(maxparam = 30))) + else: + print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30))) + for i in range(100): + print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60))) + print('endmodule') + with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): + print('read_verilog uut_%05d.v' % idx) + print('rename uut_%05d uut_%05d_syn' % (idx, idx)) + print('write_verilog uut_%05d_syn.v' % idx) + with file('temp/uut_%05d_tb.v' % idx, 'w') as f, redirect_stdout(f): + print('module uut_%05d_tb;\n' % idx) + print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)]))) + print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)]))) + print('uut_%05d ref(%s);' % (idx, ', '.join(['r%02d' % i for i in range(100)]))) + print('uut_%05d_syn syn(%s);' % (idx, ', '.join(['s%02d' % i for i in range(100)]))) + print('task compare_ref_syn;') + print(' input [7:0] i;') + print(' input [63:0] r, s;') + print(' reg [64*8-1:0] buffer;') + print(' integer j;') + print(' begin') + print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin') + print(' // $display("%d: %b %b", i, r, s);') + print(' end else if (r === s) begin ') + print(' // $display("%d: %b %b", i, r, s);') + print(' end else begin ') + print(' for (j = 0; j < 64; j = j+1)') + print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";') + print(' $display("\\n%3d: %b %b", i, r, s);') + print(' $display(" %s %s", buffer, buffer);') + print(' end') + print(' end') + print('endtask') + print('initial begin #1;') + for i in range(100): + print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i)) + print('end') + print('endmodule') + diff --git a/tests/realmath/run-test.sh b/tests/realmath/run-test.sh new file mode 100755 index 000000000..b8e222ad6 --- /dev/null +++ b/tests/realmath/run-test.sh @@ -0,0 +1,24 @@ +#!/bin/bash +set -e + +rm -rf temp +mkdir -p temp +echo "generating tests.." +python generate.py + +cd temp +echo "running tests.." +for ((i = 0; i < 100; i++)); do + echo -n "[$i]" + idx=$( printf "%05d" $i ) + ../../../yosys -q uut_${idx}.ys + iverilog -o uut_${idx}_tb uut_${idx}_tb.v uut_${idx}.v uut_${idx}_syn.v + ./uut_${idx}_tb | tee uut_${idx}.err + if test -s uut_${idx}.err; then + echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog." + exit 1 + fi + rm -f uut_${idx}.err +done +echo + diff --git a/tests/sat/asserts.ys b/tests/sat/asserts.ys index de5e7c9aa..d8f994925 100644 --- a/tests/sat/asserts.ys +++ b/tests/sat/asserts.ys @@ -1,3 +1,3 @@ -read_verilog asserts.v +read_verilog -sv asserts.v hierarchy; proc; opt sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts diff --git a/tests/sat/asserts_seq.ys b/tests/sat/asserts_seq.ys index c622ef610..e97686644 100644 --- a/tests/sat/asserts_seq.ys +++ b/tests/sat/asserts_seq.ys @@ -1,4 +1,4 @@ -read_verilog asserts_seq.v +read_verilog -sv asserts_seq.v hierarchy; proc; opt sat -verify -prove-asserts -tempinduct -seq 1 test_001 diff --git a/tests/sat/initval.v b/tests/sat/initval.v new file mode 100644 index 000000000..5b661f8d6 --- /dev/null +++ b/tests/sat/initval.v @@ -0,0 +1,15 @@ +module test(input clk, input [3:0] bar, output [3:0] foo); + reg [3:0] foo = 0; + reg [3:0] last_bar = 0; + + always @* + foo[1:0] <= bar[1:0]; + + always @(posedge clk) + foo[3:2] <= bar[3:2]; + + always @(posedge clk) + last_bar <= bar; + + assert property (foo == {last_bar[3:2], bar[1:0]}); +endmodule diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys new file mode 100644 index 000000000..2079d2f34 --- /dev/null +++ b/tests/sat/initval.ys @@ -0,0 +1,4 @@ +read_verilog -sv initval.v +proc;; + +sat -seq 10 -prove-asserts diff --git a/tests/sat/share.v b/tests/sat/share.v new file mode 100644 index 000000000..e06fc8f1e --- /dev/null +++ b/tests/sat/share.v @@ -0,0 +1,32 @@ +module test_1( + input [7:0] a, b, c, + input s, x, + output [7:0] y1, y2 +); + wire [7:0] t1, t2; + assign t1 = s ? a*b : 0, t2 = !s ? b*c : 0; + assign y1 = x ? t2 : t1, y2 = x ? t1 : t2; +endmodule + + +module test_2( + input s, + input [7:0] a, b, c, + output reg [7:0] y +); + always @* begin + y <= 'bx; + if (s) begin + if (a * b > 8) + y <= b / c; + else + y <= c / b; + end else begin + if (b * c > 8) + y <= a / b; + else + y <= b / a; + end + end +endmodule + diff --git a/tests/sat/share.ys b/tests/sat/share.ys new file mode 100644 index 000000000..f2f5d649d --- /dev/null +++ b/tests/sat/share.ys @@ -0,0 +1,17 @@ +read_verilog share.v +proc;; + +copy test_1 gold_1 +copy test_2 gold_2 +share test_1 test_2;; + +select -assert-count 1 test_1/t:$mul +select -assert-count 1 test_2/t:$mul +select -assert-count 1 test_2/t:$div + +miter -equiv -flatten -make_outputs -make_outcmp gold_1 test_1 miter_1 +sat -verify -prove trigger 0 -show-inputs -show-outputs miter_1 + +miter -equiv -flatten -make_outputs -make_outcmp gold_2 test_2 miter_2 +sat -verify -prove trigger 0 -show-inputs -show-outputs miter_2 + diff --git a/tests/share/.gitignore b/tests/share/.gitignore new file mode 100644 index 000000000..9c595a6fb --- /dev/null +++ b/tests/share/.gitignore @@ -0,0 +1 @@ +temp diff --git a/tests/share/generate.py b/tests/share/generate.py new file mode 100644 index 000000000..a06a642d8 --- /dev/null +++ b/tests/share/generate.py @@ -0,0 +1,73 @@ +#!/usr/bin/python + +from __future__ import division +from __future__ import print_function + +import sys +import random +from contextlib import contextmanager + +@contextmanager +def redirect_stdout(new_target): + old_target, sys.stdout = sys.stdout, new_target + try: + yield new_target + finally: + sys.stdout = old_target + +def random_plus_x(): + return "%s x" % random.choice(['+', '+', '+', '-', '-', '|', '&', '^']) + +def maybe_plus_x(expr): + if random.randint(0, 4) == 0: + return "(%s %s)" % (expr, random_plus_x()) + else: + return expr + +for idx in range(100): + with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f): + if random.choice(['bin', 'uni']) == 'bin': + print('module uut_%05d(a, b, c, d, x, s, y);' % (idx)) + op = random.choice([ + random.choice(['+', '-', '*', '/', '%']), + random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]), + random.choice(['<<', '>>', '<<<', '>>>']), + random.choice(['|', '&', '^', '~^', '||', '&&']), + ]) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' % + (random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'), + random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'), + random_plus_x() if random.randint(0, 4) == 0 else '')) + print('endmodule') + else: + print('module uut_%05d(a, b, x, s, y);' % (idx)) + op = random.choice(['~', '-', '!']) + print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8))) + print(' input s;') + print(' output [%d:0] y;' % random.randint(0, 8)) + print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' % + (random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'), + random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'), + random_plus_x() if random.randint(0, 4) == 0 else '')) + print('endmodule') + with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f): + print('read_verilog temp/uut_%05d.v' % idx) + print('proc;;') + print('copy uut_%05d gold' % idx) + print('rename uut_%05d gate' % idx) + print('tee -a temp/all_share_log.txt log') + print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx) + print('tee -a temp/all_share_log.txt wreduce') + print('tee -a temp/all_share_log.txt share -aggressive gate') + print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') + print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') + diff --git a/tests/share/run-test.sh b/tests/share/run-test.sh new file mode 100755 index 000000000..203d6fcd7 --- /dev/null +++ b/tests/share/run-test.sh @@ -0,0 +1,27 @@ +#!/bin/bash + +# run this test many times: +# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done' + +set -e + +rm -rf temp +mkdir -p temp +echo "generating tests.." +python generate.py + +echo "running tests.." +for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do + echo -n "[$i]" + idx=$( printf "%05d" $i ) + ../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys +done +echo + +failed_share=$( echo $( gawk '/^#job#/ { j=$2; db[j]=0; } /^Removing [24] cells/ { delete db[j]; } END { for (j in db) print(j); }' temp/all_share_log.txt ) ) +if [ -n "$failed_share" ]; then + echo "Resource sharing failed for the following test cases: $failed_share" + false +fi + +exit 0 diff --git a/tests/simple/arraycells.v b/tests/simple/arraycells.v new file mode 100644 index 000000000..704ca3fda --- /dev/null +++ b/tests/simple/arraycells.v @@ -0,0 +1,15 @@ + +module array_test001(a, b, c, y); + input a; + input [31:0] b, c; + input [31:0] y; + + aoi12 p [31:0] (a, b, c, y); +endmodule + +module aoi12(a, b, c, y); + input a, b, c; + output y; + assign y = ~((a & b) | c); +endmodule + diff --git a/tests/simple/forgen01.v b/tests/simple/forgen01.v index 70ee7e667..8b7aa279d 100644 --- a/tests/simple/forgen01.v +++ b/tests/simple/forgen01.v @@ -1,3 +1,6 @@ + +// VERIFIC-SKIP + module uut_forgen01(a, y); input [4:0] a; diff --git a/tests/simple/fsm.v b/tests/simple/fsm.v index 79ca041dd..2dba14bb0 100644 --- a/tests/simple/fsm.v +++ b/tests/simple/fsm.v @@ -1,7 +1,7 @@ // `define ASYNC_RESET -module test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b); +module fsm_test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b); input clk, reset, button_a, button_b; output reg red_a, green_a, red_b, green_b; diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 39e573a73..24eb4462c 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -1,5 +1,5 @@ -module test1(clk, a, b, y); +module gen_test1(clk, a, b, y); input clk; input [7:0] a, b; @@ -40,7 +40,7 @@ endmodule // ------------------------------------------ -module test2(clk, a, b, y); +module gen_test2(clk, a, b, y); input clk; input [7:0] a, b; @@ -67,7 +67,7 @@ endmodule // ------------------------------------------ -module test3(a, b, sel, y, z); +module gen_test3(a, b, sel, y, z); input [3:0] a, b; input sel; diff --git a/tests/simple/i2c_master_tests.v b/tests/simple/i2c_master_tests.v index f8f564085..3aa596632 100644 --- a/tests/simple/i2c_master_tests.v +++ b/tests/simple/i2c_master_tests.v @@ -3,7 +3,7 @@ // this core that triggered bugs in early versions of yosys. // from i2c_master_bit_ctrl -module test01(clk, rst, nReset, al); +module i2c_test01(clk, rst, nReset, al); input clk, rst, nReset; output reg al; @@ -26,7 +26,7 @@ module test01(clk, rst, nReset, al); endmodule // from i2c_master_bit_ctrl -module test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt); +module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt); input clk, slave_wait, clk_cnt; input cmd; diff --git a/tests/simple/macros.v b/tests/simple/macros.v index cda46cb48..7b4d616ea 100644 --- a/tests/simple/macros.v +++ b/tests/simple/macros.v @@ -235,3 +235,10 @@ always @* begin end endmodule + +`define SIZE 4 // comment supported in this part +module test_comment_in_macro ( din_a, dout_a ); +input [`SIZE-1:0] din_a; +output [`SIZE-1:0] dout_a; +assign dout_a = din_a | `SIZE'ha; +endmodule diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index e2c136ddb..bed5528d4 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -1,5 +1,5 @@ -module test1(in_addr, in_data, out_addr, out_data); +module mem2reg_test1(in_addr, in_data, out_addr, out_data); input [1:0] in_addr, out_addr; input [3:0] in_data; @@ -19,7 +19,7 @@ endmodule // ------------------------------------------------------ -module test2(clk, mode, addr, data); +module mem2reg_test2(clk, mode, addr, data); input clk, mode; input [2:0] addr; @@ -43,3 +43,15 @@ end endmodule +// ------------------------------------------------------ + +// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/ +module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b); +reg [7:0] dint_c [0:7]; +always @(posedge clk) + begin + {dout_a[0], dint_c[3]} <= din_a; + end +assign dout_b = dint_c[3]; +endmodule + diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v index 4022f57cd..9bd38fcb3 100644 --- a/tests/simple/mem_arst.v +++ b/tests/simple/mem_arst.v @@ -10,7 +10,7 @@ module MyMem #( output [DataWidth-1:0] Data_o, input WR_i); - reg Data_o; + reg [DataWidth-1:0] Data_o; localparam Size = 2**AddrWidth; diff --git a/tests/simple/memory.v b/tests/simple/memory.v index 927ee0438..db06c56d2 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -1,5 +1,5 @@ -module test00(clk, setA, setB, y); +module memtest00(clk, setA, setB, y); input clk, setA, setB; output y; @@ -16,7 +16,7 @@ endmodule // ---------------------------------------------------------- -module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value); +module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value); input clk, wr_en; input [3:0] wr_addr, rd_addr; @@ -36,7 +36,7 @@ endmodule // ---------------------------------------------------------- -module test02(clk, setA, setB, addr, bit, y1, y2, y3, y4); +module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4); input clk, setA, setB; input [1:0] addr; @@ -77,7 +77,7 @@ endmodule // ---------------------------------------------------------- -module test03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); +module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); input clk, wr_enable; input [3:0] wr_addr, wr_data, rd_addr; @@ -95,7 +95,7 @@ endmodule // ---------------------------------------------------------- -module test04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); +module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); input clk, wr_enable; input [3:0] wr_addr, wr_data, rd_addr; @@ -114,3 +114,94 @@ assign rd_data = memory[rd_addr_buf]; endmodule +// ---------------------------------------------------------- + +module memtest05(clk, addr, wdata, rdata, wen); + +input clk; +input [1:0] addr; +input [7:0] wdata; +output reg [7:0] rdata; +input [3:0] wen; + +reg [7:0] mem [0:3]; + +integer i; +always @(posedge clk) begin + for (i = 0; i < 4; i = i+1) + if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2]; + rdata <= mem[addr]; +end + +endmodule + +// ---------------------------------------------------------- + +module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); + (* gentb_constant=0 *) wire rst; + reg [7:0] test [0:7]; + integer i; + always @(posedge clk) begin + if (rst) begin + for (i=0; i<8; i=i+1) + test[i] <= 0; + end else begin + test[0][2] <= din[1]; + test[0][5] <= test[0][2]; + test[idx][3] <= din[idx]; + test[idx][6] <= test[idx][2]; + test[idx][idx] <= !test[idx][idx]; + end + end + assign dout = test[idx]; +endmodule + +module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); + (* gentb_constant=0 *) wire rst; + reg [7:0] test [0:7]; + integer i; + always @(posedge clk or posedge rst) begin + if (rst) begin + for (i=0; i<8; i=i+1) + test[i] <= 0; + end else begin + test[0][2] <= din[1]; + test[0][5] <= test[0][2]; + test[idx][3] <= din[idx]; + test[idx][6] <= test[idx][2]; + test[idx][idx] <= !test[idx][idx]; + end + end + assign dout = test[idx]; +endmodule + +// ---------------------------------------------------------- + +module memtest07(clk, addr, woffset, wdata, rdata); + +input clk; +input [1:0] addr; +input [3:0] wdata; +input [1:0] woffset; +output reg [7:0] rdata; + +reg [7:0] mem [0:3]; + +integer i; +always @(posedge clk) begin + mem[addr][woffset +: 4] <= wdata; + rdata <= mem[addr]; +end + +endmodule + +// ---------------------------------------------------------- + +module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y); + reg [3:0] mem [0:15] [0:15]; + always @(posedge clk) begin + y <= mem[a][b]; + mem[a][b] <= c; + end +endmodule + diff --git a/tests/simple/operators.v b/tests/simple/operators.v index 7439101c8..2f0fdb820 100644 --- a/tests/simple/operators.v +++ b/tests/simple/operators.v @@ -1,4 +1,4 @@ -module test(clk, mode, u1, s1, u2, s2, y); +module optest(clk, mode, u1, s1, u2, s2, y); input clk; input [6:0] mode; diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v index 8d0134a67..23cb276f2 100644 --- a/tests/simple/paramods.v +++ b/tests/simple/paramods.v @@ -1,5 +1,5 @@ -module test1(a, b, x, y); +module pm_test1(a, b, x, y); input [7:0] a, b; output [7:0] x, y; @@ -11,7 +11,7 @@ endmodule // ----------------------------------- -module test2(a, b, x, y); +module pm_test2(a, b, x, y); input [7:0] a, b; output [7:0] x, y; @@ -23,7 +23,7 @@ endmodule // ----------------------------------- -module test3(a, b, x, y); +module pm_test3(a, b, x, y); input [7:0] a, b; output [7:0] x, y; diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v index acfc1ca5d..7461358ad 100644 --- a/tests/simple/partsel.v +++ b/tests/simple/partsel.v @@ -1,5 +1,62 @@ -module test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down); +module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down); wire [5:0] offset = idx << 2; assign slice_up = data[offset +: 4]; assign slice_down = data[offset + 3 -: 4]; endmodule + +module partsel_test002 ( + input clk, rst, + input [7:0] a, + input [0:7] b, + input [1:0] s, + output [7:0] x1, x2, x3, + output [0:7] x4, x5, x6, + output [7:0] y1, y2, y3, + output [0:7] y4, y5, y6, + output [7:0] z1, z2, z3, + output [0:7] z4, z5, z6, + output [7:0] w1, w2, w3, + output [0:7] w4, w5, w6, + output [7:0] p1, p2, p3, p4, p5, p6, + output [0:7] q1, q2, q3, q4, q5, q6, + output reg [7:0] r1, + output reg [0:7] r2 +); + +assign x1 = a, x2 = a + b, x3 = b; +assign x4 = a, x5 = a + b, x6 = b; +assign y1 = a[4 +: 3], y2 = a[4 +: 3] + b[4 +: 3], y3 = b[4 +: 3]; +assign y4 = a[4 +: 3], y5 = a[4 +: 3] + b[4 +: 3], y6 = b[4 +: 3]; +assign z1 = a[4 -: 3], z2 = a[4 -: 3] + b[4 -: 3], z3 = b[4 -: 3]; +assign z4 = a[4 -: 3], z5 = a[4 -: 3] + b[4 -: 3], z6 = b[4 -: 3]; +assign w1 = a[6:3], w2 = a[6:3] + b[3:6], w3 = b[3:6]; +assign w4 = a[6:3], w5 = a[6:3] + b[3:6], w6 = b[3:6]; +assign p1 = a[s], p2 = b[s], p3 = a[s+2 +: 2], p4 = b[s+2 +: 2], p5 = a[s+2 -: 2], p6 = b[s+2 -: 2]; +assign q1 = a[s], q2 = b[s], q3 = a[s+2 +: 2], q4 = b[s+2 +: 2], q5 = a[s+2 -: 2], q6 = b[s+2 -: 2]; + +always @(posedge clk) begin + if (rst) begin + { r1, r2 } = 16'h1337 ^ {a, b}; + end else begin + case (s) + 0: begin + r1[3:0] <= r2[0:3] ^ x1; + r2[4:7] <= r1[7:4] ^ x4; + end + 1: begin + r1[2 +: 3] <= r2[5 -: 3] + x1; + r2[3 +: 3] <= r1[6 -: 3] + x4; + end + 2: begin + r1[6 -: 3] <= r2[3 +: 3] - x1; + r2[7 -: 3] <= r1[4 +: 3] - x4; + end + 3: begin + r1 <= r2; + r2 <= r1; + end + endcase + end +end + +endmodule diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v new file mode 100644 index 000000000..5b756e6be --- /dev/null +++ b/tests/simple/realexpr.v @@ -0,0 +1,24 @@ + +module demo_001(y1, y2, y3, y4); + output [7:0] y1, y2, y3, y4; + + localparam [7:0] p1 = 123.45; + localparam real p2 = 123.45; + localparam real p3 = 123; + localparam p4 = 123.45; + + assign y1 = p1 + 0.2; + assign y2 = p2 + 0.2; + assign y3 = p3 + 0.2; + assign y4 = p4 + 0.2; +endmodule + +module demo_002(y0, y1, y2, y3); + output [63:0] y0, y1, y2, y3; + + assign y0 = 1'bx >= (-1 * -1.17); + assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0; + assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0; + assign y3 = 1 ? -1 : 'd0; +endmodule + diff --git a/tests/simple/repwhile.v b/tests/simple/repwhile.v new file mode 100644 index 000000000..5d0c75fa6 --- /dev/null +++ b/tests/simple/repwhile.v @@ -0,0 +1,36 @@ +module repwhile_test001(input [5:0] a, output [7:0] y, output [31:0] x); + + function [7:0] mylog2; + input [31:0] value; + begin + mylog2 = 0; + while (value > 0) begin + value = value >> 1; + mylog2 = mylog2 + 1; + end + end + endfunction + + function [31:0] myexp2; + input [7:0] value; + begin + myexp2 = 1; + repeat (value) + myexp2 = myexp2 << 1; + end + endfunction + + reg [7:0] y_table [63:0]; + reg [31:0] x_table [63:0]; + + integer i; + initial begin + for (i = 0; i < 64; i = i+1) begin + y_table[i] <= mylog2(i); + x_table[i] <= myexp2(i); + end + end + + assign y = y_table[a]; + assign x = x_table[a]; +endmodule diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh index eb6fd10ba..6531d51ae 100755 --- a/tests/simple/run-test.sh +++ b/tests/simple/run-test.sh @@ -6,5 +6,4 @@ if ! which iverilog > /dev/null ; then exit 1 fi -make -C ../.. || exit 1 -exec bash ../tools/autotest.sh *.v +exec ${MAKE:-make} -f ../tools/autotest.mk *.v diff --git a/tests/simple/scopes.v b/tests/simple/scopes.v new file mode 100644 index 000000000..eecc1a0b2 --- /dev/null +++ b/tests/simple/scopes.v @@ -0,0 +1,63 @@ +module scopes_test_01(input [3:0] k, output reg [15:0] x, y); + function [15:0] func_01; + input [15:0] x, y; + begin + func_01 = x + y; + begin:blk + reg [15:0] x; + x = y; + func_01 = func_01 ^ x; + end + func_01 = func_01 ^ x; + end + endfunction + + function [15:0] func_02; + input [15:0] x, y; + begin + func_02 = x - y; + begin:blk + reg [15:0] func_02; + func_02 = 0; + end + end + endfunction + + task task_01; + input [3:0] a; + reg [15:0] y; + begin + y = a * 23; + x = x + y; + end + endtask + + task task_02; + input [3:0] a; + begin:foo + reg [15:0] x, z; + x = y; + begin:bar + reg [15:0] x; + x = 77 + a; + z = -x; + end + y = x ^ z; + end + endtask + + always @* begin + x = func_01(11, 22); + y = func_02(33, 44); + task_01(k); + task_02(k); + begin:foo + reg [15:0] y; + y = x; + y = y + k; + x = y; + end + x = func_01(y, x); + y = func_02(y, x); + end +endmodule diff --git a/tests/simple/signedexpr.v b/tests/simple/signedexpr.v index 3eb5e93df..8bba4a4b1 100644 --- a/tests/simple/signedexpr.v +++ b/tests/simple/signedexpr.v @@ -1,4 +1,4 @@ -module test01(a, b, xu, xs, yu, ys, zu, zs); +module signed_test01(a, b, xu, xs, yu, ys, zu, zs); input signed [1:0] a; input signed [2:0] b; diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v index 3a09cbc35..51e31015f 100644 --- a/tests/simple/task_func.v +++ b/tests/simple/task_func.v @@ -1,5 +1,5 @@ -module test01(clk, a, b, c, x, y, z, w); +module task_func_test01(clk, a, b, c, x, y, z, w); input clk; input [7:0] a, b, c; @@ -33,3 +33,16 @@ end endmodule + +module task_func_test02( input [7:0] din_a, input [7:0] din_b, output [7:0] dout_a); + assign dout_a = test(din_a,din_b); + function [7:0] test; + input [7:0] a; + input [7:0] b; + begin : TEST + integer i; + for (i = 0; i <= 7; i = i + 1) + test[i] = a[i] & b[i]; + end + endfunction +endmodule diff --git a/tests/simple/undef_eqx_nex.v b/tests/simple/undef_eqx_nex.v index 63912a2fa..b0178677b 100644 --- a/tests/simple/undef_eqx_nex.v +++ b/tests/simple/undef_eqx_nex.v @@ -1,4 +1,4 @@ -module test(y); +module undef_eqx_nex(y); output [7:0] y; assign y[0] = 0/0; assign y[1] = 0/1; diff --git a/tests/simple/usb_phy_tetsts.v b/tests/simple/usb_phy_tests.v index 2375183d8..bc45e71a5 100644 --- a/tests/simple/usb_phy_tetsts.v +++ b/tests/simple/usb_phy_tests.v @@ -1,6 +1,6 @@ // from usb_rx_phy -module test01(clk, rst, rx_en, fs_ce); +module usb_phy_test01(clk, rst, rx_en, fs_ce); input clk, rst; input rx_en; diff --git a/tests/techmap/.gitignore b/tests/techmap/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/techmap/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/techmap/mem_simple_4x1_cells.v b/tests/techmap/mem_simple_4x1_cells.v new file mode 100644 index 000000000..7ecdd2dee --- /dev/null +++ b/tests/techmap/mem_simple_4x1_cells.v @@ -0,0 +1,13 @@ +module MEM4X1 (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); + input CLK, WR_DATA, WR_EN; + input [3:0] RD_ADDR, WR_ADDR; + output reg RD_DATA; + + reg [15:0] memory; + + always @(posedge CLK) begin + if (WR_EN) + memory[WR_ADDR] <= WR_DATA; + RD_DATA <= memory[RD_ADDR]; + end +endmodule diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v new file mode 100644 index 000000000..820f89de4 --- /dev/null +++ b/tests/techmap/mem_simple_4x1_map.v @@ -0,0 +1,140 @@ + +module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA); + parameter MEMID = ""; + parameter SIZE = 256; + parameter OFFSET = 0; + parameter ABITS = 8; + parameter WIDTH = 8; + + parameter RD_PORTS = 1; + parameter RD_CLK_ENABLE = 1'b1; + parameter RD_CLK_POLARITY = 1'b1; + parameter RD_TRANSPARENT = 1'b1; + + parameter WR_PORTS = 1; + parameter WR_CLK_ENABLE = 1'b1; + parameter WR_CLK_POLARITY = 1'b1; + + input [RD_PORTS-1:0] RD_CLK; + input [RD_PORTS*ABITS-1:0] RD_ADDR; + output reg [RD_PORTS*WIDTH-1:0] RD_DATA; + + input [WR_PORTS-1:0] WR_CLK; + input [WR_PORTS*WIDTH-1:0] WR_EN; + input [WR_PORTS*ABITS-1:0] WR_ADDR; + input [WR_PORTS*WIDTH-1:0] WR_DATA; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + parameter _TECHMAP_CONNMAP_RD_CLK_ = 0; + parameter _TECHMAP_CONNMAP_WR_CLK_ = 0; + + parameter _TECHMAP_BITS_CONNMAP_ = 0; + parameter _TECHMAP_CONNMAP_WR_EN_ = 0; + + reg _TECHMAP_FAIL_; + integer k; + initial begin + _TECHMAP_FAIL_ <= 0; + + // only map cells with only one read and one write port + if (RD_PORTS > 1 || WR_PORTS > 1) + _TECHMAP_FAIL_ <= 1; + + // we expect positive read clock and non-transparent reads + if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY) + _TECHMAP_FAIL_ <= 1; + + // we expect positive write clock + if (!WR_CLK_ENABLE || !WR_CLK_POLARITY) + _TECHMAP_FAIL_ <= 1; + + // only one global write enable bit is supported + for (k = 1; k < WR_PORTS*WIDTH; k = k+1) + if (_TECHMAP_CONNMAP_WR_EN_[0 +: _TECHMAP_BITS_CONNMAP_] != + _TECHMAP_CONNMAP_WR_EN_[k*_TECHMAP_BITS_CONNMAP_ +: _TECHMAP_BITS_CONNMAP_]) + _TECHMAP_FAIL_ <= 1; + + // read and write must be in same clock domain + if (_TECHMAP_CONNMAP_RD_CLK_ != _TECHMAP_CONNMAP_WR_CLK_) + _TECHMAP_FAIL_ <= 1; + + // we don't do small memories or memories with offsets + if (OFFSET != 0 || ABITS < 4 || SIZE < 16) + _TECHMAP_FAIL_ <= 1; + end + + genvar i; + generate + for (i = 0; i < WIDTH; i=i+1) begin:slice + \$__mem_4x1_generator #( + .ABITS(ABITS), + .SIZE(SIZE) + ) bit_slice ( + .CLK(RD_CLK), + .RD_ADDR(RD_ADDR), + .RD_DATA(RD_DATA[i]), + .WR_ADDR(WR_ADDR), + .WR_DATA(WR_DATA[i]), + .WR_EN(WR_EN[0]) + ); + end + endgenerate +endmodule + +module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); + parameter ABITS = 4; + parameter SIZE = 16; + + input CLK, WR_DATA, WR_EN; + input [ABITS-1:0] RD_ADDR, WR_ADDR; + output RD_DATA; + + wire [1023:0] _TECHMAP_DO_ = "proc; clean"; + + generate + if (ABITS > 4) begin + wire high_rd_data, low_rd_data; + if (SIZE > 2**(ABITS-1)) begin + \$__mem_4x1_generator #( + .ABITS(ABITS-1), + .SIZE(SIZE - 2**(ABITS-1)) + ) part_high ( + .CLK(CLK), + .RD_ADDR(RD_ADDR[ABITS-2:0]), + .RD_DATA(high_rd_data), + .WR_ADDR(WR_ADDR[ABITS-2:0]), + .WR_DATA(WR_DATA), + .WR_EN(WR_EN && WR_ADDR[ABITS-1]) + ); + end else begin + assign high_rd_data = 1'bx; + end + \$__mem_4x1_generator #( + .ABITS(ABITS-1), + .SIZE(SIZE > 2**(ABITS-1) ? 2**(ABITS-1) : SIZE) + ) part_low ( + .CLK(CLK), + .RD_ADDR(RD_ADDR[ABITS-2:0]), + .RD_DATA(low_rd_data), + .WR_ADDR(WR_ADDR[ABITS-2:0]), + .WR_DATA(WR_DATA), + .WR_EN(WR_EN && !WR_ADDR[ABITS-1]) + ); + reg delayed_abit; + always @(posedge CLK) + delayed_abit <= RD_ADDR[ABITS-1]; + assign RD_DATA = delayed_abit ? high_rd_data : low_rd_data; + end else begin + MEM4X1 _TECHMAP_REPLACE_ ( + .CLK(CLK), + .RD_ADDR(RD_ADDR), + .RD_DATA(RD_DATA), + .WR_ADDR(WR_ADDR), + .WR_DATA(WR_DATA), + .WR_EN(WR_EN) + ); + end + endgenerate +endmodule + diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh new file mode 100644 index 000000000..e2c6303da --- /dev/null +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +set -ev + +../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v + +iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v +iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v + +./mem_simple_4x1_gold_tb > mem_simple_4x1_gold_tb.out +./mem_simple_4x1_gate_tb > mem_simple_4x1_gate_tb.out + +diff -u mem_simple_4x1_gold_tb.out mem_simple_4x1_gate_tb.out +rm -f mem_simple_4x1_synth.v mem_simple_4x1_tb.vcd +rm -f mem_simple_4x1_{gold,gate}_tb{,.out} +: OK + diff --git a/tests/techmap/mem_simple_4x1_tb.v b/tests/techmap/mem_simple_4x1_tb.v new file mode 100644 index 000000000..532626960 --- /dev/null +++ b/tests/techmap/mem_simple_4x1_tb.v @@ -0,0 +1,29 @@ +module tb; + +reg clk, rst; +wire [7:0] out; +wire [4:0] counter; + +uut uut (clk, rst, out, counter); + +initial begin + #5 clk <= 0; + repeat (100) #5 clk <= ~clk; + #5 $finish; +end + +initial begin + rst <= 1; + repeat (2) @(posedge clk); + rst <= 0; +end + +always @(posedge clk) + $display("%d %d %d", rst, out, counter); + +initial begin + $dumpfile("mem_simple_4x1_tb.vcd"); + $dumpvars(0, uut); +end + +endmodule diff --git a/tests/techmap/mem_simple_4x1_uut.v b/tests/techmap/mem_simple_4x1_uut.v new file mode 100644 index 000000000..8d4614595 --- /dev/null +++ b/tests/techmap/mem_simple_4x1_uut.v @@ -0,0 +1,15 @@ +module uut (clk, rst, out, counter); + +input clk, rst; +output reg [7:0] out; +output reg [4:0] counter; + +reg [7:0] memory [0:19]; + +always @(posedge clk) begin + counter <= rst || counter == 19 ? 0 : counter+1; + memory[counter] <= counter; + out <= memory[counter]; +end + +endmodule diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh new file mode 100755 index 000000000..e2fc11e52 --- /dev/null +++ b/tests/techmap/run-test.sh @@ -0,0 +1,10 @@ +#!/bin/bash +set -e +for x in *_runtest.sh; do + echo "Running $x.." + if ! bash $x &> ${x%.sh}.log; then + tail ${x%.sh}.log + echo ERROR + exit 1 + fi +done diff --git a/tests/tools/autotest.mk b/tests/tools/autotest.mk new file mode 100644 index 000000000..f65002cef --- /dev/null +++ b/tests/tools/autotest.mk @@ -0,0 +1,8 @@ + +EXTRA_FLAGS= + +$(MAKECMDGOALS): + @$(basename $(MAKEFILE_LIST)).sh -G -j $(EXTRA_FLAGS) $@ + +.PHONY: $(MAKECMDGOALS) + diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 7bccd9a5a..50f5cb580 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -6,38 +6,52 @@ use_xsim=false use_modelsim=false verbose=false keeprunning=false +makejmode=false +frontend="verilog" backend_opts="-noattr -noexpr" +autotb_opts="" scriptfiles="" scriptopt="" toolsdir="$(cd $(dirname $0); pwd)" +warn_iverilog_git=false if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then ( set -ex; gcc -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 fi -while getopts xml:wkvrs:p: opt; do +while getopts xmGl:wkjvref:s:p:n: opt; do case "$opt" in x) use_xsim=true ;; m) use_modelsim=true ;; + G) + warn_iverilog_git=true ;; l) libs="$libs $(cd $(dirname $OPTARG); pwd)/$(basename $OPTARG)";; w) genvcd=true ;; k) keeprunning=true ;; + j) + makejmode=true ;; v) verbose=true ;; r) backend_opts="$backend_opts -norename" ;; + e) + backend_opts="$( echo " $backend_opts " | sed 's, -noexpr ,,; s,^ ,,; s, $,,;'; )" ;; + f) + frontend="$OPTARG" ;; s) [[ "$OPTARG" == /* ]] || OPTARG="$PWD/$OPTARG" scriptfiles="$scriptfiles $OPTARG" ;; p) scriptopt="$OPTARG" ;; + n) + autotb_opts="$autotb_opts -n $OPTARG" ;; *) - echo "Usage: $0 [-x|-m] [-w] [-k] [-v] [-r] [-l libs] [-s script] [-p cmdstring] verilog-files\n" >&2 + echo "Usage: $0 [-x|-m] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] verilog-files\n" >&2 exit 1 esac done @@ -77,17 +91,26 @@ do exit 1 fi [[ "$bn" == *_tb ]] && continue - echo -n "Test: $bn " - rm -f ${bn}.{err,log} + if $makejmode; then + status_prefix="Test: $bn " + else + status_prefix="" + echo -n "Test: $bn " + fi + + rm -f ${bn}.{err,log,sikp} mkdir -p ${bn}.out rm -rf ${bn}.out/* body() { cd ${bn}.out + fn=$(basename $fn) + bn=$(basename $bn) + cp ../$fn $fn if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -b autotest -o ${bn}_tb.v $fn + "$toolsdir"/../../yosys -b "test_autotb $autotb_opts" -o ${bn}_tb.v $fn else cp ../${bn}_tb.v ${bn}_tb.v fi @@ -98,7 +121,7 @@ do test_count=0 test_passes() { - "$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles + "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@" compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ ${bn}_tb.v ${bn}_syn${test_count}.v $libs \ "$toolsdir"/../../techlibs/common/simlib.v \ @@ -108,13 +131,22 @@ do test_count=$(( test_count + 1 )) } + if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP $fn; then + touch ../${bn}.skip + return + fi + if [ -n "$scriptfiles" ]; then - test_passes + test_passes $fn $scriptfiles elif [ -n "$scriptopt" ]; then - test_passes -p "$scriptopt" + test_passes -f "$frontend" -p "$scriptopt" $fn + elif [ "$frontend" = "verific" ]; then + test_passes -p "verific -vlog2k $fn; verific -import -all; opt; memory;;" + elif [ "$frontend" = "verific_gates" ]; then + test_passes -p "verific -vlog2k $fn; verific -import -gates -all; opt; memory;;" else - test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt" - test_passes -p "hierarchy; proc; opt; memory; opt; fsm; opt; techmap; opt; abc -dff; opt" + test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -fine" $fn + test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" $fn fi touch ../${bn}.log } @@ -129,8 +161,17 @@ do if [ -f ${bn}.log ]; then mv ${bn}.err ${bn}.log - echo "-> ok" - else echo "-> ERROR!"; $keeprunning || exit 1; fi + echo "${status_prefix}-> ok" + elif [ -f ${bn}.skip ]; then + mv ${bn}.err ${bn}.skip + echo "${status_prefix}-> skip" + else + echo "${status_prefix}-> ERROR!" + if $warn_iverilog_git; then + echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of icarus verilog." + fi + $keeprunning || exit 1 + fi done exit 0 diff --git a/tests/tools/txt2tikztiming.py b/tests/tools/txt2tikztiming.py new file mode 100755 index 000000000..cfefe339f --- /dev/null +++ b/tests/tools/txt2tikztiming.py @@ -0,0 +1,109 @@ +#!/usr/bin/python + +from __future__ import division +from __future__ import print_function + +import argparse +import fileinput +import sys + +parser = argparse.ArgumentParser(description='Convert vcd2txt output to tikz-timing line.') +parser.add_argument('filename', metavar='FILE', help='input txt file') +parser.add_argument('signame', metavar='SIG', help='Signal name') +parser.add_argument('-s', metavar='scale', default=1.0, type=float, help='Scale all time spans with this factor') +parser.add_argument('-l', action='store_true', help='Logic signal (high/low)') +parser.add_argument('-b', action='store_true', help='Display binary value') +parser.add_argument('-x', action='store_true', help='Display hex value') +parser.add_argument('-d', action='store_true', help='Display decimal value') +args = parser.parse_args() + +start_time = None +stop_time = None +time_val = { } + +def value_to_logic(value): + found_x = False + for char in value: + if char == '1': + return "H" + if char == 'x': + found_x = True + return "U" if found_x else "L" + +def value_to_binary(value): + return "D{%s}" % value + +def value_to_hex(value): + hex_string = "" + found_def = False + while len(value) % 4 != 0: + value = "0" + value + while len(value) != 0: + bin_digits = value[0:4] + hex_digit = 0 + value = value[4:] + for b in bin_digits: + if b == '0': + hex_digit = hex_digit * 2 + elif b == '1': + hex_digit = hex_digit * 2 + 1 + else: + hex_digit += 100 + if hex_digit > 15: + hex_string += "x" + else: + found_def = True + hex_string += "0123456789abcdef"[hex_digit] + if not found_def: + return "U"; + return "D{%s}" % hex_string + +def value_to_decimal(value): + val = 0 + found_def = False + found_undef = False + for digit in value: + if digit == 'x': + found_undef = True + else: + val = val*2 + int(digit) + found_def = True + if found_def: + if found_undef: + return "D{X}" + else: + return "D{%d}" % val + return "U" + +for line in fileinput.input(args.filename): + (node, time, name, value) = line.strip().split('\t') + time = int(time) + if start_time is None or start_time > time: + start_time = time + if stop_time is None or stop_time < time: + stop_time = time + if name == args.signame: + if args.l: + time_val[+time] = value_to_logic(value) + elif args.b: + time_val[+time] = value_to_binary(value) + elif args.x: + time_val[+time] = value_to_hex(value) + elif args.d: + time_val[+time] = value_to_decimal(value) + else: + time_val[+time] = value + +if start_time not in time_val: + time_val[start_time] = "S" + +last_time = None +last_value = None +for t in sorted(time_val.keys()): + if last_time is not None: + print("%f%s" % ((t - last_time)*args.s, last_value), end='') + (last_time, last_value) = (t, time_val[t]) +if last_time < stop_time: + print("%f%s" % ((stop_time - last_time)*args.s, last_value), end='') +print('') + diff --git a/tests/tools/vcd2txt.pl b/tests/tools/vcd2txt.pl new file mode 100755 index 000000000..92d3d1652 --- /dev/null +++ b/tests/tools/vcd2txt.pl @@ -0,0 +1,61 @@ +#!/usr/bin/perl -w +# +# Note: You might need to install the Verilog::VCD package using CPAN.. + +use strict; +use Data::Dumper; +use Verilog::VCD qw(parse_vcd list_sigs); + +$| = 1; + +my $from_time = -1; +my $to_time = -1; + +while (1) +{ + if ($ARGV[0] eq '-f') { + $from_time = +$ARGV[1]; + shift @ARGV; + shift @ARGV; + next; + } + if ($ARGV[0] eq '-t') { + $to_time = +$ARGV[1]; + shift @ARGV; + shift @ARGV; + next; + } + last; +} + +if ($#ARGV < 0) { + print STDERR "\n"; + print STDERR "VCD2TXT - Convert VCD to tab-separated text file\n"; + print STDERR "\n"; + print STDERR "Usage: $0 [-f from_time] [-t to_time] input.vcd [<signal regex> ...]\n"; + print STDERR "\n"; + exit 1; +} + +my $vcd = parse_vcd($ARGV[0]); + +for my $node (keys $vcd) { + for my $net (@{$vcd->{$node}->{'nets'}}) { + my $dump_this = $#ARGV == 0; + for (my $i = 1; $i <= $#ARGV; $i++) { + my $regex = $ARGV[$i]; + $dump_this = 1 if ($net->{"hier"} . "." . $net->{"name"}) =~ /$regex/; + } + next unless $dump_this; + my $cached_value = ""; + for my $tv (@{$vcd->{$node}->{'tv'}}) { + $cached_value = $tv->[1], next if $from_time >= 0 and +$tv->[0] < $from_time; + next if $to_time >= 0 and +$tv->[0] > $to_time; + printf "%s\t%s\t%s\t%s\n", $node, $from_time, $net->{"hier"} . "." . $net->{"name"}, $cached_value + if $cached_value ne "" and $from_time >= 0 and +$tv->[0] > $from_time; + printf "%s\t%s\t%s\t%s\n", $node, $tv->[0], $net->{"hier"} . "." . $net->{"name"}, $tv->[1]; + $cached_value = ""; + } + } +} + diff --git a/tests/various/.gitignore b/tests/various/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/various/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/various/constmsk_test.v b/tests/various/constmsk_test.v new file mode 100644 index 000000000..0d0e58fef --- /dev/null +++ b/tests/various/constmsk_test.v @@ -0,0 +1,4 @@ +module test(input [3:0] A, output [3:0] Y1, Y2); + assign Y1 = |{A[3], 1'b0, A[1]}; + assign Y2 = |{A[2], 1'b1, A[0]}; +endmodule diff --git a/tests/various/constmsk_test.ys b/tests/various/constmsk_test.ys new file mode 100644 index 000000000..ce36efc35 --- /dev/null +++ b/tests/various/constmsk_test.ys @@ -0,0 +1,15 @@ +read_verilog constmsk_test.v + +copy test gold +rename test gate + +cd gate +techmap -map constmsk_testmap.v;; +cd .. + +select -assert-count 2 gold/r:A_WIDTH=3 +select -assert-count 1 gate/r:A_WIDTH=2 +select -assert-count 1 gate/c:* + +miter -equiv -flatten gold gate miter +sat -verify -prove trigger 0 miter diff --git a/tests/various/constmsk_testmap.v b/tests/various/constmsk_testmap.v new file mode 100644 index 000000000..fab1b1bbc --- /dev/null +++ b/tests/various/constmsk_testmap.v @@ -0,0 +1,49 @@ +(* techmap_celltype = "$reduce_or" *) +module my_opt_reduce_or(...); + parameter A_SIGNED = 0; + parameter A_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + output reg [Y_WIDTH-1:0] Y; + + parameter _TECHMAP_CONSTMSK_A_ = 0; + parameter _TECHMAP_CONSTVAL_A_ = 0; + + wire _TECHMAP_FAIL_ = count_nonconst_bits() == A_WIDTH; + wire [1024:0] _TECHMAP_DO_ = "proc;;"; + + function integer count_nonconst_bits; + integer i; + begin + count_nonconst_bits = 0; + for (i = 0; i < A_WIDTH; i=i+1) + if (!_TECHMAP_CONSTMSK_A_[i]) + count_nonconst_bits = count_nonconst_bits+1; + end + endfunction + + function has_const_one; + integer i; + begin + has_const_one = 0; + for (i = 0; i < A_WIDTH; i=i+1) + if (_TECHMAP_CONSTMSK_A_[i] && _TECHMAP_CONSTVAL_A_[i] === 1'b1) + has_const_one = 1; + end + endfunction + + integer i; + reg [count_nonconst_bits()-1:0] tmp; + + always @* begin + if (has_const_one()) begin + Y = 1; + end else begin + for (i = 0; i < A_WIDTH; i=i+1) + if (!_TECHMAP_CONSTMSK_A_[i]) + tmp = {A[i], tmp[count_nonconst_bits()-1:1]}; + Y = |tmp; + end + end +endmodule diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh new file mode 100755 index 000000000..67e1beb23 --- /dev/null +++ b/tests/various/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.ys; do + echo "Running $x.." + ../../yosys -ql ${x%.ys}.log $x +done diff --git a/tests/various/submod_extract.ys b/tests/various/submod_extract.ys new file mode 100644 index 000000000..8d11c21d3 --- /dev/null +++ b/tests/various/submod_extract.ys @@ -0,0 +1,21 @@ +read_verilog << EOT + module test(input [7:0] a, b, c, d, output [7:0] x, y, z); + assign x = a + b, y = b + c, z = c + d; + endmodule +EOT + +copy test gold +rename test gate + +submod -name mycell gate/x %ci* +design -copy-to mymap mycell +extract -map %mymap gate + +select -assert-count 3 gold/t:* +select -assert-count 3 gold/t:$add + +select -assert-count 3 gate/t:* +select -assert-count 3 gate/t:mycell + +miter -equiv -flatten gold gate miter +sat -verify -prove trigger 0 miter diff --git a/tests/vloghtb/.gitignore b/tests/vloghtb/.gitignore new file mode 100644 index 000000000..63db2fba3 --- /dev/null +++ b/tests/vloghtb/.gitignore @@ -0,0 +1,9 @@ +Makefile +refdat +rtl +scripts +spec +check_yosys +vloghammer_tb.tar.bz2 +temp +log_test_* diff --git a/tests/vloghtb/common.sh b/tests/vloghtb/common.sh new file mode 100644 index 000000000..3965b04ca --- /dev/null +++ b/tests/vloghtb/common.sh @@ -0,0 +1,70 @@ +log_pass() +{ + printf "%-15s %s %s %s\n" "$1" "$2" "`printf "%20s" "$2" | tr -d a-zA-Z0-9_ | tr ' ' .`" "pass." +} + +log_fail() +{ + printf "%-15s %s %s %s\n" "$1" "$2" "`printf "%20s" "$2" | tr -d a-zA-Z0-9_ | tr ' ' .`" "FAIL." +} + +test_autotest() +{ + # Usage: + # test_autotest <test_name> <synth_script> <mod_name> <vlog_file> + + test_name="$1" + synth_cmd="$2" + mod_name="$3" + vlog_file="$4" + + mkdir -p log_test_$test_name + rm -rf log_test_$test_name/$mod_name.* + + ../../yosys -q -l log_test_$test_name/$mod_name.out -o log_test_$test_name/$mod_name.v -p "$synth_cmd" "$vlog_file" + cat spec/${mod_name}_spec.v scripts/check.v >> log_test_$test_name/$mod_name.v + iverilog -o log_test_$test_name/$mod_name.bin -D"REFDAT_FN=\"refdat/${mod_name}_refdat.txt\"" log_test_$test_name/$mod_name.v + + if log_test_$test_name/$mod_name.bin 2>&1 | tee -a log_test_$test_name/$mod_name.out | grep -q '++OK++'; then + mv log_test_$test_name/$mod_name.out log_test_$test_name/$mod_name.txt + log_pass test_$test_name $mod_name + else + mv log_test_$test_name/$mod_name.out log_test_$test_name/$mod_name.err + log_fail test_$test_name $mod_name + exit 1 + fi +} + +test_equiv() +{ + # Usage: + # test_equiv <test_name> <synth_script> <sat_options> <mod_name> <vlog_file> + + mkdir -p log_test_$1 + rm -f log_test_$1/$4.txt + rm -f log_test_$1/$4.err + + if ! ../../yosys -q -l log_test_$1/$4.out - 2> /dev/null <<- EOT + read_verilog $5 + proc;; + + copy $4 gold + rename $4 work + + cd work + $2 + cd .. + + miter -equiv -ignore_gold_x -make_outputs -make_outcmp gold work miter + flatten miter + sat $3 -verify -prove trigger 0 -show-inputs -show-outputs miter + EOT + then + log_fail test_$1 $4 + mv log_test_$1/$4.out log_test_$1/$4.err + exit 1 + fi + + log_pass test_$1 $4 + mv log_test_$1/$4.out log_test_$1/$4.txt +} diff --git a/tests/vloghtb/run-test.sh b/tests/vloghtb/run-test.sh new file mode 100755 index 000000000..ad99226e7 --- /dev/null +++ b/tests/vloghtb/run-test.sh @@ -0,0 +1,15 @@ +#!/bin/bash + +set -ex + +rm -rf Makefile refdat rtl scripts spec +wget -N http://www.clifford.at/yosys/nogit/vloghammer_tb.tar.bz2 +tar --strip=1 -xjf vloghammer_tb.tar.bz2 + +make clean +rm -rf log_test_* + +${MAKE:-make} EXIT_ON_ERROR=1 YOSYS_BIN=$PWD/../../yosys YOSYS_SCRIPT="proc;;" check_yosys +${MAKE:-make} -f test_makefile MODE=share +${MAKE:-make} -f test_makefile MODE=mapopt + diff --git a/tests/vloghtb/test_makefile b/tests/vloghtb/test_makefile new file mode 100644 index 000000000..174dbbc2c --- /dev/null +++ b/tests/vloghtb/test_makefile @@ -0,0 +1,9 @@ + +MODE := share +TESTS := $(shell ls rtl/ | sed 's,\.v$$,,' ) + +run: $(addprefix log_test_$(MODE)/,$(addsuffix .txt,$(TESTS))) + +log_test_$(MODE)/%.txt: rtl/%.v + @bash test_$(MODE).sh $< + diff --git a/tests/vloghtb/test_mapopt.sh b/tests/vloghtb/test_mapopt.sh new file mode 100644 index 000000000..61528c2b4 --- /dev/null +++ b/tests/vloghtb/test_mapopt.sh @@ -0,0 +1,17 @@ +#!/bin/bash + +set -e +source common.sh + +f=$1 +n=$(basename ${f%.v}) + +mkdir -p log_test_mapopt +rm -f log_test_mapopt/$n.* + +test_equiv mapopt_1 "opt -fine; techmap; opt" "-set-def-inputs" $n $f +test_autotest mapopt_2 "proc; opt; techmap; opt" $n $f + +tail -n20 log_test_mapopt_1/$n.txt log_test_mapopt_2/$n.txt > log_test_mapopt/$n.txt + +exit 0 diff --git a/tests/vloghtb/test_share.sh b/tests/vloghtb/test_share.sh new file mode 100644 index 000000000..67cfe44e8 --- /dev/null +++ b/tests/vloghtb/test_share.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e +source common.sh + +f=$1 +n=$(basename ${f%.v}) + +test_equiv share "wreduce; share -aggressive" "-ignore_div_by_zero" $n $f + +exit 0 |