| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | Avoid tristate warning for blackbox ice40/cells_sim.v | Clifford Wolf | 2015-07-18 | 1 | -0/+2 | |
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| * | | Some fixes in "select" command | Clifford Wolf | 2015-07-16 | 1 | -1/+3 | |
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| * | | Fixed YosysJS.create_worker() usage of this.url_prefix | Clifford Wolf | 2015-07-10 | 1 | -1/+1 | |
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| * | | Improved liberty file test case | Clifford Wolf | 2015-07-06 | 1 | -1/+2 | |
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| * | | Updated ABC | Clifford Wolf | 2015-07-06 | 1 | -1/+1 | |
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| * | | Do not collect disabled $memwr cells | Clifford Wolf | 2015-07-06 | 1 | -15/+18 | |
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| * | | Improved YosysJS WebWorker API | Clifford Wolf | 2015-07-04 | 3 | -10/+51 | |
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| * | | Bugfix in fsm_extract | Clifford Wolf | 2015-07-03 | 1 | -3/+16 | |
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| * | | Added "synth -nofsm" | Clifford Wolf | 2015-07-02 | 1 | -1/+10 | |
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| * | | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 195 | -729/+729 | |
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| * | | Added opt_const -clkinv | Clifford Wolf | 2015-07-01 | 2 | -6/+95 | |
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| * | | Added logic-loop error handling to freduce | Clifford Wolf | 2015-06-30 | 1 | -0/+11 | |
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| * | | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2015-06-30 | 3 | -33/+145 | |
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| | * | | Added YosysJS.create_worker() | Clifford Wolf | 2015-06-28 | 3 | -33/+145 | |
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| * | | | Bugfix in chparam | Clifford Wolf | 2015-06-30 | 1 | -6/+5 | |
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| * | | | Added design->rename(module, new_name) | Clifford Wolf | 2015-06-30 | 3 | -3/+9 | |
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| * | | iCE40: set min bram efficiency to 2% | Clifford Wolf | 2015-06-20 | 1 | -2/+2 | |
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| * | | Using static mem size of 128 MB in emcc build | Clifford Wolf | 2015-06-20 | 1 | -1/+1 | |
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| * | | Added init support to SMV back-end | Clifford Wolf | 2015-06-19 | 1 | -1/+3 | |
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| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-19 | 1 | -64/+115 | |
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| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-19 | 2 | -14/+60 | |
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| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-18 | 4 | -24/+147 | |
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| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-17 | 1 | -11/+72 | |
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| * | | Added "rename -top new_name" | Clifford Wolf | 2015-06-17 | 3 | -0/+43 | |
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| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-17 | 1 | -11/+64 | |
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| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-16 | 1 | -3/+46 | |
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| * | | Added "synth -nordff -noalumacc" | Clifford Wolf | 2015-06-15 | 1 | -3/+20 | |
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| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-15 | 1 | -2/+95 | |
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| * | | Progress in SMV back-end | Clifford Wolf | 2015-06-15 | 1 | -7/+85 | |
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| * | | Added "write_smv" skeleton | Clifford Wolf | 2015-06-15 | 3 | -2/+265 | |
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| * | | Removed debug code from write_smt2 | Clifford Wolf | 2015-06-14 | 1 | -2/+0 | |
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| * | | Modernized memory_dff (and fixed a bug) | Clifford Wolf | 2015-06-14 | 2 | -151/+166 | |
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| * | | Added "memory -nordff" | Clifford Wolf | 2015-06-14 | 1 | -2/+9 | |
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| * | | Added write_smt2 -mem | Clifford Wolf | 2015-06-14 | 1 | -80/+157 | |
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| * | | Makefile fix for YosysJS build | Clifford Wolf | 2015-06-11 | 1 | -0/+4 | |
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| * | | Fixed cstr_buf for std::string with small string optimization | Clifford Wolf | 2015-06-11 | 6 | -5/+16 | |
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| * | | Improvements in cellaigs.cc and "json -aig" | Clifford Wolf | 2015-06-11 | 2 | -10/+215 | |
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| * | | AigMaker refactoring | Clifford Wolf | 2015-06-10 | 4 | -78/+153 | |
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| * | | Added "json -aig" | Clifford Wolf | 2015-06-10 | 3 | -9/+76 | |
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| * | | Renamed "aig" to "aigmap" | Clifford Wolf | 2015-06-10 | 3 | -10/+10 | |
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| * | | Fixed cellaigs port extending | Clifford Wolf | 2015-06-10 | 3 | -3/+11 | |
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| * | | Added "aig" pass | Clifford Wolf | 2015-06-09 | 3 | -16/+291 | |
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| * | | synth_ice40 now flattens by default | Clifford Wolf | 2015-06-09 | 1 | -4/+8 | |
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| * | | Added cellaigs API | Clifford Wolf | 2015-06-09 | 4 | -2/+173 | |
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| * | | Merge clock inverters in memory_dff | Clifford Wolf | 2015-06-09 | 1 | -16/+37 | |
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| * | | Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys | Clifford Wolf | 2015-06-09 | 1 | -54/+110 | |
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| | * | | $mem cell in verilog backend : grouped writes by clock | luke whittlesey | 2015-06-08 | 2 | -58/+110 | |
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| | * | | Bug fix in $mem verilog backend + changed tests/bram flow of make test. | luke whittlesey | 2015-06-04 | 2 | -16/+20 | |
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| * | | | Fixed "avail_parameters" handling in module clone/copy | Clifford Wolf | 2015-06-08 | 1 | -0/+2 | |
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| * | | | Added log_dump() support for IdStrings | Clifford Wolf | 2015-06-08 | 2 | -0/+5 | |
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index : iCE40/yosys | |
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