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* | Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-181-34/+72
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* | Added "via_celltype" attribute on task/funcClifford Wolf2014-08-183-18/+110
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* | Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-181-7/+5
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* | Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-181-61/+31
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* | Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-183-1/+41
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* | Fixed proc_{self,share}_dirname error handlingClifford Wolf2014-08-171-4/+2
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* | Makefile fixesClifford Wolf2014-08-171-1/+4
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* | Improved AST ProcessGenerator performanceClifford Wolf2014-08-171-3/+3
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* | Improved sig.remove2() performanceClifford Wolf2014-08-171-2/+11
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* | Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-173-24/+22
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* | Added stackmap<> containerClifford Wolf2014-08-172-2/+109
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* | Renamed toposort.h to utils.hClifford Wolf2014-08-173-2/+2
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* | Added module->uniquify()Clifford Wolf2014-08-165-15/+29
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* | Fixed AOI/OAI expr handling in verilog backendClifford Wolf2014-08-161-4/+4
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* | Multiply using a carry-save accumulatorClifford Wolf2014-08-161-5/+45
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* | Added "test_cell -s <seed>"Clifford Wolf2014-08-161-5/+17
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* | AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-161-41/+26
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* | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-168-48/+399
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* | Added CellTypes::cell_evaluable()Clifford Wolf2014-08-161-31/+37
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* | Changes in techmap $__alu interfaceClifford Wolf2014-08-161-17/+17
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* | Added "opt -fast"Clifford Wolf2014-08-161-19/+45
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* | Added log_spacer()Clifford Wolf2014-08-163-2/+20
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* | Bugfix in iopadmapClifford Wolf2014-08-151-1/+3
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* | Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-156-39/+38
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* | Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-1519-47/+47
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* | Removed old doc references to $safe_pmuxClifford Wolf2014-08-152-5/+1
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* | More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-154-10/+22
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* | Added Frontend "+/" filename syntax for files from proc_share_dirClifford Wolf2014-08-151-1/+4
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* | document "techmap -map %<design-name>"Clifford Wolf2014-08-151-0/+3
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* | Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
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* | Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-143-11/+20
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* | Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-143-21/+31
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* | Added sig.{replace,remove,extract} variants for std::{map,set} patternClifford Wolf2014-08-142-25/+64
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* | Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
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* | Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
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* | Simplified $__arraymul techmap ruleClifford Wolf2014-08-141-7/+13
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* | Added module->portsClifford Wolf2014-08-149-10/+23
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* | Refactoring of CellType classClifford Wolf2014-08-143-155/+139
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* | RIP $safe_pmuxClifford Wolf2014-08-1416-98/+21
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* | Some improvements in FSM mapping and recodingClifford Wolf2014-08-143-9/+18
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* | Added "abc -D" for setting delay targetClifford Wolf2014-08-141-5/+18
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* | Updated ABC to 4935c2b946deClifford Wolf2014-08-141-1/+1
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* | Added techmap support for actual lookahead carry unitClifford Wolf2014-08-131-22/+73
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* | Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-131-28/+92
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* | Filter ANSI escape sequences from ABC outputClifford Wolf2014-08-131-0/+15
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* | New interface for $__alu in techmap.vClifford Wolf2014-08-131-129/+62
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* | Added support for non-standard """ macro bodiesClifford Wolf2014-08-132-1/+21
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* | Fixed handling of constant-true branches in proc_cleanClifford Wolf2014-08-122-2/+3
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* | Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-121-7/+17
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* | Fixed SigBit(RTLIL::Wire *wire) constructorClifford Wolf2014-08-121-1/+1
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