| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | | * | | | | | | | Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results | Eddie Hung | 2019-06-07 | 1 | -1/+64 | |
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| | | * | | | | | | | Add @cliffordwolf freduce testcase | Eddie Hung | 2019-06-07 | 2 | -0/+30 | |
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| | | * | | | | | | | Add nonexclusive test from @cliffordwolf | Eddie Hung | 2019-06-07 | 2 | -0/+28 | |
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| | | * | | | | | | | Resolve @cliffordwolf comment on redundant check | Eddie Hung | 2019-06-07 | 1 | -10/+2 | |
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| | | * | | | | | | | Resolve @cliffordwolf comment on sigmap | Eddie Hung | 2019-06-07 | 1 | -2/+2 | |
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| | | * | | | | | | | Another muxpack test | Eddie Hung | 2019-06-07 | 2 | -0/+32 | |
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| * | | | | | | | | | nullptr check | Eddie Hung | 2019-06-25 | 1 | -0/+1 | |
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| * | | | | | | | | | Use LUT delays for dist RAM delays | Eddie Hung | 2019-06-24 | 1 | -4/+4 | |
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| * | | | | | | | | | Fix for abc_scc_break is bus | Eddie Hung | 2019-06-24 | 1 | -21/+23 | |
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| * | | | | | | | | | More meaningful error message | Eddie Hung | 2019-06-24 | 1 | -0/+2 | |
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| * | | | | | | | | | Re-enable dist RAM boxes for ECP5 | Eddie Hung | 2019-06-24 | 1 | -1/+1 | |
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| * | | | | | | | | | Revert "Re-enable dist RAM boxes for ECP5" | Eddie Hung | 2019-06-24 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ca0225fcfaa8c9c68647034351a1569464959edf. | |||||
| * | | | | | | | | | Do not use log_id as it strips \\, also fix scc for |wire| > 1 | Eddie Hung | 2019-06-24 | 1 | -13/+30 | |
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| * | | | | | | | | | Re-enable dist RAM boxes for ECP5 | Eddie Hung | 2019-06-24 | 1 | -1/+1 | |
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| * | | | | | | | | | Add Xilinx dist RAM as comb boxes | Eddie Hung | 2019-06-24 | 2 | -0/+16 | |
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| * | | | | | | | | | Fix abc9's scc breaker, also break on abc_scc_break attr | Eddie Hung | 2019-06-24 | 1 | -9/+31 | |
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| * | | | | | | | | | Add tests/various/abc9.{v,ys} with SCC test | Eddie Hung | 2019-06-24 | 2 | -0/+19 | |
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-24 | 2 | -0/+16 | |
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| | * | | | | | | | | Merge pull request #1124 from mmicko/json_ports | Clifford Wolf | 2019-06-24 | 2 | -0/+16 | |
| | |\ \ \ \ \ \ \ \ | | |_|_|_|_|_|/ / | |/| | | | | | | | Add upto and offset to JSON ports | |||||
| | | * | | | | | | | Fix json formatting | Miodrag Milanovic | 2019-06-21 | 1 | -1/+1 | |
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| | | * | | | | | | | Add upto and offset to JSON ports | Miodrag Milanovic | 2019-06-21 | 2 | -0/+16 | |
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| * | | | | | | | | | Add comments to ecp5 box | Eddie Hung | 2019-06-22 | 1 | -0/+6 | |
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| * | | | | | | | | | Add comment to xc7 box | Eddie Hung | 2019-06-22 | 1 | -0/+3 | |
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| * | | | | | | | | | Fix and cleanup ice40 boxes for carry in/out | Eddie Hung | 2019-06-22 | 4 | -313/+25 | |
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| * | | | | | | | | | Carry in/out box ordering now move to end, not swap with end | Eddie Hung | 2019-06-22 | 2 | -38/+46 | |
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| * | | | | | | | | | Remove DFF and RAMD box info for now | Eddie Hung | 2019-06-21 | 2 | -36/+0 | |
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| * | | | | | | | | | Merge branch 'master' into xaig | Eddie Hung | 2019-06-21 | 1 | -1/+3 | |
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| | * | | | | | | | | Add 'muxcover -dmux=<cost>' and '-nopartial' to CHANGELOG | Eddie Hung | 2019-06-21 | 1 | -1/+3 | |
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| * | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-21 | 15 | -59/+446 | |
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| | * | | | | | | | | Merge pull request #1108 from YosysHQ/clifford/fix1091 | Eddie Hung | 2019-06-21 | 2 | -46/+239 | |
| | |\ \ \ \ \ \ \ \ | | |/ / / / / / / | |/| | | | | | | | Add support for partial matches to muxcover | |||||
| | | * | | | | | | | Replace "muxcover -freedecode" with "muxcover -dmux=cost" | Clifford Wolf | 2019-06-21 | 1 | -15/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | Add "muxcover -freedecode" | Clifford Wolf | 2019-06-21 | 1 | -0/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | Improvements in muxcover | Clifford Wolf | 2019-06-20 | 1 | -38/+55 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Slightly under-estimate cost of decoder muxes - Prefer larger muxes at tree root at same cost - Don't double-count input cost for partial muxes - Add debug log output | |||||
| | | * | | | | | | | Missing a `clean` and `opt_expr -mux_bool` in test | Eddie Hung | 2019-06-20 | 1 | -0/+4 | |
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| | | * | | | | | | | Add test | Eddie Hung | 2019-06-20 | 1 | -1/+136 | |
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| | | * | | | | | | | Add support for partial matches to muxcover, fixes #1091 | Clifford Wolf | 2019-06-20 | 1 | -7/+31 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | | Merge pull request #1123 from mmicko/fix_typo | Clifford Wolf | 2019-06-21 | 1 | -1/+1 | |
| | |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Fix json frontend loading upto | |||||
| | | * | | | | | | | | Fix typo | Miodrag Milanovic | 2019-06-21 | 1 | -1/+1 | |
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| | * | | | | | | | | Merge pull request #1085 from YosysHQ/eddie/shregmap_improve | Eddie Hung | 2019-06-21 | 3 | -3/+129 | |
| | |\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | Improve shregmap to handle case where first flop is common to two chains | |||||
| | | * | | | | | | | | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-06-20 | 1 | -3/+1 | |
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| | | * | | | | | | | | Add comment as per @cliffordwolf | Eddie Hung | 2019-06-20 | 1 | -0/+11 | |
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| | | * | | | | | | | | Add shregmap -tech xilinx test | Eddie Hung | 2019-06-12 | 2 | -2/+63 | |
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| | | * | | | | | | | | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-06-11 | 1 | -15/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. | |||||
| | * | | | | | | | | | Merge pull request #1122 from YosysHQ/clifford/jsonports | Clifford Wolf | 2019-06-21 | 2 | -0/+16 | |
| | |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Added JSON upto and offset | |||||
| | | * | | | | | | | | | Added JSON upto and offset | Clifford Wolf | 2019-06-21 | 2 | -0/+16 | |
| | |/ / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | | | Merge pull request #1121 from YosysHQ/ecp5-ccu2c-inv | Clifford Wolf | 2019-06-21 | 1 | -4/+5 | |
| | |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | ecp5: Improve mapping of $alu when BI is used | |||||
| | | * | | | | | | | | | ecp5: Improve mapping of $alu when BI is used | David Shah | 2019-06-21 | 1 | -4/+5 | |
| | |/ / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | * | | | | | | | | | Merge pull request #1117 from bwidawsk/more-home | Clifford Wolf | 2019-06-21 | 2 | -0/+5 | |
| | |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | Add a few more filename rewrites | |||||
| | | * | | | | | | | | | Add a few more filename rewrites | Ben Widawsky | 2019-06-20 | 2 | -0/+5 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This now allows a full pipeline to work, something such as: yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v" Otherwise, you will get something along the lines of: ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory Signed-off-by: Ben Widawsky <ben@bwidawsk.net> | |||||
| | * | | | | | | | | | | Merge pull request #1119 from YosysHQ/eddie/fix1118 | Clifford Wolf | 2019-06-21 | 2 | -0/+12 | |
| | |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | Make genvar a signed type | |||||
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