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* | | Added RTLIL::ObjIterator and RTLIL::ObjRange | Clifford Wolf | 2014-07-27 | 2 | -7/+111 | |
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* | | Using std::move() in SigSpec move constructor | Clifford Wolf | 2014-07-27 | 1 | -4/+4 | |
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* | | Added RTLIL::SigSpec move constructor and move assignment operator | Clifford Wolf | 2014-07-27 | 1 | -0/+15 | |
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* | | Mostly cosmetic changes to rtlil.h | Clifford Wolf | 2014-07-27 | 1 | -17/+57 | |
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* | | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 61 | -152/+152 | |
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* | | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 50 | -191/+191 | |
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* | | New message for completion of build | Clifford Wolf | 2014-07-26 | 1 | -1/+1 | |
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* | | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 8 | -81/+52 | |
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* | | Changed a lot of code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 19 | -218/+150 | |
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* | | Added tests/various/.gitignore | Clifford Wolf | 2014-07-26 | 1 | -0/+1 | |
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* | | Added tests/various/submod_extract.ys | Clifford Wolf | 2014-07-26 | 3 | -0/+28 | |
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* | | Added support for here documents | Clifford Wolf | 2014-07-26 | 3 | -18/+63 | |
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* | | More RTLIL::Cell API usage cleanups | Clifford Wolf | 2014-07-26 | 5 | -39/+39 | |
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* | | Added RTLIL::Cell::has(portname) | Clifford Wolf | 2014-07-26 | 12 | -27/+33 | |
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* | | Merge automatic and manual code changes for new cell connections API | Clifford Wolf | 2014-07-26 | 61 | -1201/+1247 | |
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| * | | Manual fixes for new cell connections API | Clifford Wolf | 2014-07-26 | 36 | -123/+169 | |
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| * | | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 61 | -1201/+1201 | |
|/ / | | | | | | | | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | |||||
* | | Added some missing "const" in rtlil.h | Clifford Wolf | 2014-07-26 | 2 | -9/+9 | |
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* | | Added RTLIL::Module::connections() | Clifford Wolf | 2014-07-26 | 2 | -0/+6 | |
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* | | Added RTLIL::Module::connect(const RTLIL::SigSig&) | Clifford Wolf | 2014-07-26 | 2 | -0/+6 | |
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* | | Use "wget -N" in tests/vloghtb/run-test.sh | Clifford Wolf | 2014-07-26 | 1 | -2/+2 | |
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* | | Added "passed" message to make test targets | Clifford Wolf | 2014-07-26 | 1 | -0/+9 | |
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* | | Automatically pack SigSpec on copy/assign | Clifford Wolf | 2014-07-26 | 2 | -17/+63 | |
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* | | Added new RTLIL::Cell port access methods | Clifford Wolf | 2014-07-26 | 2 | -0/+71 | |
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* | | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 62 | -1213/+1234 | |
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* | | Cosmetic fixes for "make abc" | Clifford Wolf | 2014-07-26 | 1 | -2/+3 | |
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* | | Added "Checklist for adding internal cell types" | Clifford Wolf | 2014-07-26 | 1 | -2/+26 | |
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* | | Added copy-constructor-like module->addCell(name, other) method | Clifford Wolf | 2014-07-26 | 4 | -20/+17 | |
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* | | Use only module->addCell() and module->remove() to create and delete cells | Clifford Wolf | 2014-07-25 | 35 | -582/+259 | |
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* | | Various RTLIL::SigSpec related code cleanups | Clifford Wolf | 2014-07-25 | 4 | -47/+55 | |
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* | | Added RTLIL::SigSpec is_chunk()/as_chunk() API | Clifford Wolf | 2014-07-25 | 2 | -0/+20 | |
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* | | Added "make vgtest" | Clifford Wolf | 2014-07-25 | 1 | -0/+5 | |
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* | | Fixed two memory leaks in ast simplify | Clifford Wolf | 2014-07-25 | 1 | -1/+6 | |
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* | | Renamed some of the test cases in tests/simple to avoid name collisions | Clifford Wolf | 2014-07-25 | 15 | -30/+30 | |
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* | | Fixed memory corruption in "opt_reduce" pass | Clifford Wolf | 2014-07-25 | 1 | -5/+7 | |
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* | | Disabled cover() for non-linux builds | Clifford Wolf | 2014-07-25 | 3 | -4/+8 | |
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* | | Added more stuff to checklist | Clifford Wolf | 2014-07-25 | 1 | -0/+4 | |
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* | | Updated verific build/test instructions | Clifford Wolf | 2014-07-25 | 2 | -13/+11 | |
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* | | Improvements in "cover" command | Clifford Wolf | 2014-07-25 | 1 | -11/+37 | |
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* | | Removed Minisat dependency on zlib | Clifford Wolf | 2014-07-25 | 5 | -13/+43 | |
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* | | Added more stuff to the checklist | Clifford Wolf | 2014-07-25 | 1 | -1/+13 | |
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* | | Fixed typo in cover id | Clifford Wolf | 2014-07-25 | 1 | -1/+1 | |
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* | | Added "make clean-abc" | Clifford Wolf | 2014-07-25 | 1 | -0/+4 | |
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* | | Further improved "make" prettiness | Clifford Wolf | 2014-07-25 | 1 | -5/+10 | |
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* | | Replaced more old SigChunk programming patterns | Clifford Wolf | 2014-07-24 | 17 | -104/+101 | |
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* | | Updated ABC to hg id "b1e63d18768d" | Clifford Wolf | 2014-07-24 | 1 | -1/+1 | |
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* | | Added cover() calls to opt_const | Clifford Wolf | 2014-07-24 | 1 | -9/+45 | |
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* | | Added cover_list() API | Clifford Wolf | 2014-07-24 | 2 | -2/+46 | |
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* | | Added "make SMALL=1" | Clifford Wolf | 2014-07-24 | 2 | -1/+30 | |
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* | | Now "make PRETTY=1" is the default setting | Clifford Wolf | 2014-07-24 | 1 | -5/+7 | |
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