Commit message (Collapse) | Author | Age | Files | Lines | |
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* | iopadmap: Fix z assignment to inout port | Marcin KoĆcielnicki | 2020-04-02 | 2 | -2/+24 |
| | | | | Fixes #1841. | ||||
* | Merge pull request #1842 from YosysHQ/mwk/fix-deminout-xz | Claire Wolf | 2020-04-02 | 1 | -1/+1 |
|\ | | | | | deminout: prevent any constant assignment from demoting to input | ||||
| * | deminout: prevent any constant assignment from demoting to input | Marcin KoĆcielnicki | 2020-03-30 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this patch, ``` module top(inout io); assign io = 1'bx; endmodule ``` would have the `io` pin demoted to input (same happens for `1'bz`, but not for `1'b0` or `1'b1`), resulting in check failures later on. Part of fix for #1841. | ||||
* | | Merge pull request #1845 from YosysHQ/eddie/kernel_speedup | Eddie Hung | 2020-04-02 | 20 | -588/+566 |
|\ \ | | | | | | | kernel: speedup by using more pass-by-const-ref | ||||
| * | | kernel: pass-by-value into Design::scratchpad_set_string() too | Eddie Hung | 2020-03-27 | 2 | -3/+3 |
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| * | | kernel: const Wire* overload -> Wire* !!! | Eddie Hung | 2020-03-26 | 1 | -1/+1 |
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| * | | kernel: Cell::set{Port,Param}() to pass by value, but use std::move | Eddie Hung | 2020-03-26 | 2 | -7/+7 |
| | | | | | | | | | | | | Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid | ||||
| * | | kernel: SigSpec copies to not trigger pack() | Eddie Hung | 2020-03-18 | 2 | -34/+5 |
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| * | | kernel: more pass by const ref, more speedups | Eddie Hung | 2020-03-18 | 7 | -400/+400 |
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| * | | kernel: speedup | Eddie Hung | 2020-03-18 | 1 | -30/+23 |
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| * | | kernel: use const reference for SigSet too | Eddie Hung | 2020-03-17 | 1 | -18/+18 |
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| * | | kernel: fix DeleteWireWorker | Eddie Hung | 2020-03-17 | 1 | -9/+4 |
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| * | | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 14 | -82/+96 |
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| * | | kernel: optimise Module::remove(const pool<RTLIL::Wire*>() | Eddie Hung | 2020-03-12 | 2 | -10/+9 |
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| * | | kernel: SigPool to use const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-12 | 1 | -19/+25 |
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* | | | Bump YOSYS_VER | Claire Wolf | 2020-04-02 | 1 | -1/+1 |
| | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | | Merge pull request #1770 from YosysHQ/claire/btor_symbols | Claire Wolf | 2020-04-02 | 1 | -36/+60 |
|\ \ \ | | | | | | | | | Improve write_btor symbol handling | ||||
| * | | | Improve write_btor symbol handling | Claire Wolf | 2020-03-14 | 1 | -36/+60 |
| | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | | | Merge pull request #1765 from YosysHQ/claire/btor_info | Claire Wolf | 2020-04-02 | 1 | -9/+113 |
|\| | | | | | | | | | | | Add info-file and cover features to write_btor | ||||
| * | | | Add info-file and cover features to write_btor | Claire Wolf | 2020-03-13 | 1 | -9/+113 |
| |/ / | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | | Merge pull request #1777 from YosysHQ/claire/manyhot | Claire Wolf | 2020-04-02 | 1 | -14/+146 |
|\ \ \ | | | | | | | | | Using LFSR counter for ezSAT::manyhot() | ||||
| * | | | Improve ezsat onehot encoding scheme | Claire Wolf | 2020-04-02 | 1 | -14/+28 |
| | | | | | | | | | | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
| * | | | Using LFSR counter for ezSAT::manyhot() | Claire Wolf | 2020-04-02 | 1 | -0/+118 |
|/ / / | | | | | | | | | | | | | | | | | | | | | | The only user of this API right now is the puzzle3d benchmark and it sees a slight reduction in CNF size from this, but the performance difference is within the noise of measurement on my system. Signed-off-by: Claire Wolf <claire@symbioticeda.com> | ||||
* | | | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup | Eddie Hung | 2020-04-01 | 4 | -31/+50 |
|\ \ \ | | | | | | | | | kernel: share a single CellTypes within a pass | ||||
| * | | | memory_share: fix stray brace | Eddie Hung | 2020-03-30 | 1 | -1/+0 |
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| * | | | Code review fixes | Eddie Hung | 2020-03-30 | 2 | -3/+3 |
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| * | | | Apply suggestions from code review | Eddie Hung | 2020-03-30 | 2 | -6/+2 |
| | | | | | | | | | | | | Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com> | ||||
| * | | | kernel: clear some more ShareWorker state | Eddie Hung | 2020-03-26 | 1 | -0/+4 |
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| * | | | kernel: share a single CellTypes within a pass | Eddie Hung | 2020-03-18 | 4 | -31/+51 |
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* | | | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor | Eddie Hung | 2020-04-01 | 4 | -10/+92 |
|\ \ \ | | | | | | | | | opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs | ||||
| * | | | opt_expr: fix failing $xnor test | Eddie Hung | 2020-03-20 | 1 | -2/+17 |
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| * | | | opt_expr: add failing $xnor test | Eddie Hung | 2020-03-20 | 1 | -1/+13 |
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| * | | | Simplify breaking tests/arch/*/fsm.ys tests | Eddie Hung | 2020-03-20 | 2 | -7/+3 |
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| * | | | opt_expr: fix missing brace | Eddie Hung | 2020-03-20 | 1 | -2/+4 |
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| * | | | opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests | Eddie Hung | 2020-03-19 | 1 | -0/+40 |
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| * | | | opt_expr: extend to $xnor and $_XNOR_ | Eddie Hung | 2020-03-19 | 1 | -8/+12 |
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| * | | | opt_expr: optimise 1-bit $xor or $_XOR_ with constant input | Eddie Hung | 2020-03-19 | 1 | -1/+14 |
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* | | | Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu | Eddie Hung | 2020-04-01 | 2 | -19/+114 |
|\ \ \ | | | | | | | | | opt_expr: improve performance on $alu and $sub | ||||
| * | | | opt_expr: add $alu tests | Eddie Hung | 2020-03-19 | 1 | -0/+63 |
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| * | | | opt_expr: remove redundant | Eddie Hung | 2020-03-19 | 1 | -3/+0 |
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| * | | | opt_expr: optimise $sub when both A[i] and B[i] == 1'b1 | Eddie Hung | 2020-03-19 | 1 | -9/+20 |
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| * | | | opt_expr: optimise for identity $alu-s just like $add/$sub | Eddie Hung | 2020-03-19 | 1 | -7/+31 |
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* | | | Merge pull request #1844 from YosysHQ/dave/gen-source-loc | David Shah | 2020-04-01 | 1 | -0/+6 |
|\ \ \ | | | | | | | | | verilog: Add location info for generate constructs | ||||
| * | | | verilog: Add location info for generate constructs | David Shah | 2020-04-01 | 1 | -0/+6 |
| | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | | Merge pull request #1852 from boqwxp/cleanup_synth_ice40 | Eddie Hung | 2020-04-01 | 1 | -4/+4 |
|\ \ \ \ | | | | | | | | | | | Fix indentation in `techlibs/ice40/synth_ice40.cc`. | ||||
| * | | | | Fix indentation in `techlibs/ice40/synth_ice40.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -4/+4 |
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* | | | | | Merge pull request #1849 from boqwxp/cleanup_kernel_yosys | Eddie Hung | 2020-04-01 | 1 | -14/+13 |
|\ \ \ \ \ | | | | | | | | | | | | | Clean up pseudo-private member usage in `kernel/yosys.cc`. | ||||
| * | | | | | Clean up pseudo-private member usage in `kernel/yosys.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -14/+13 |
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* | | | | | Merge pull request #1850 from boqwxp/cleanup_backends | Eddie Hung | 2020-04-01 | 7 | -103/+84 |
|\ \ \ \ \ | | | | | | | | | | | | | Cleanup pseudo-private member usage and outdated `RTLIL::id2cstr()` in backends | ||||
| * | | | | | Update `RTLIL::id2cstr()` usage to `log_id`. | Alberto Gonzalez | 2020-04-01 | 1 | -2/+2 |
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