| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | opt_mem: Remove write ports with const-0 EN. | Marcelina Kościelnicka | 2021-05-23 | 2 | -0/+46 | |
| | | | | | Fixes #2765. | |||||
| * | memory_memx: Use Mem helper. | Marcelina Kościelnicka | 2021-05-22 | 1 | -42/+31 | |
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| * | kernel/rtlil: Extract some helpers for checking memory cell types. | Marcelina Kościelnicka | 2021-05-22 | 10 | -28/+24 | |
| | | | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list. | |||||
| * | kernel/mem: Add a check() function. | Marcelina Kościelnicka | 2021-05-22 | 2 | -0/+26 | |
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| * | kernel/mem: defer port removal to emit() | Marcelina Kościelnicka | 2021-05-22 | 2 | -18/+38 | |
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| * | memory_dff: Use Mem helper. | Marcelina Kościelnicka | 2021-05-21 | 1 | -19/+26 | |
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| * | Run VS build on PRs and each push | Miodrag Milanović | 2021-05-20 | 1 | -4/+1 | |
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| * | Bump version | Marcelina Kościelnicka | 2021-05-20 | 1 | -1/+1 | |
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| * | tests/blif: Add missing gitignore | Marcelina Kościelnicka | 2021-05-20 | 1 | -0/+1 | |
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| * | Visual Studio build action | Miodrag Milanovic | 2021-05-17 | 1 | -0/+40 | |
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| * | intel_alm: Fix illegal carry chains | gatecat | 2021-05-15 | 4 | -7/+9 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | intel_alm: Add global buffer insertion | gatecat | 2021-05-15 | 19 | -45/+119 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | intel_alm: Add IO buffer insertion | gatecat | 2021-05-15 | 19 | -46/+166 | |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | |||||
| * | Change the type of current_module to Module | Rupert Swarbrick | 2021-05-13 | 2 | -24/+26 | |
| | | | | | | | | | | | | The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support. | |||||
| * | Use range-based for loop in AST::process | Rupert Swarbrick | 2021-05-13 | 1 | -21/+21 | |
| | | | | | | | No functional change: just get rid of the explicit iterator and replace (*it)-> with child->. It's even the same number of characters, but is hopefully a little easier to read. | |||||
| * | Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib. | Adam Greig | 2021-05-12 | 1 | -0/+22 | |
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| * | sv: check validity of package end label | Zachary Snow | 2021-05-10 | 2 | -0/+17 | |
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| * | blif: Use library cells' start_offset and upto for wideports. | Marcelina Kościelnicka | 2021-05-08 | 4 | -10/+54 | |
| | | | | | Fixes #2729. | |||||
| * | connect: Add -assert option, fix non-working sigmap. | Marcelina Kościelnicka | 2021-05-08 | 1 | -4/+24 | |
| | | | | | Should be useful for writing tests. | |||||
| * | opt_dff: Fix NOT gates wired in reverse. | Marcelina Kościelnicka | 2021-05-04 | 2 | -10/+15 | |
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| * | Merge pull request #2738 from mdko/xilinx-blif | Miodrag Milanović | 2021-04-27 | 1 | -1/+1 | |
| |\ | | | | | Fix use of blif name in synth_xilinx command | |||||
| | * | Fix use of blif name in synth_xilinx command | Michael Christensen | 2021-04-27 | 1 | -1/+1 | |
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| * | Merge pull request #2737 from YosysHQ/claire/fix2736 | Claire Xen | 2021-04-26 | 1 | -0/+4 | |
| |\ | | | | | Remove duplicates from conns array in JSON front-end, fixes #2736 | |||||
| | * | Remove duplicates from conns array in JSON front-end, fixes #2736 | Claire Xenia Wolf | 2021-04-26 | 1 | -0/+4 | |
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| * | Merge pull request #2669 from YosysHQ/claire/ice40defaults | Claire Xen | 2021-04-21 | 2 | -26/+62 | |
| |\ | | | | | Add input default assignments to iCE40 cell library | |||||
| | * | Add default assignments to other SB_* simulation models | Claire Xenia Wolf | 2021-04-20 | 1 | -24/+44 | |
| | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| | * | Add default assignments to SB_LUT4 | Claire Xenia Wolf | 2021-04-20 | 2 | -2/+18 | |
| |/ | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | quicklogic: ABC9 synthesis | Lofty | 2021-04-17 | 12 | -22/+97 | |
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| * | sf2: fix name of AND modules | Stefan Riesenberger | 2021-04-09 | 1 | -3/+3 | |
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| * | Merge pull request #2724 from whitequark/flatten-rewrite-memwr-memid | whitequark | 2021-04-09 | 1 | -0/+3 | |
| |\ | | | | | flatten: rewrite memid in memwr actions | |||||
| | * | flatten: rewrite memid in memwr actions. | whitequark | 2021-04-09 | 1 | -0/+3 | |
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| * | preproc: test coverage for #2712 | Zachary Snow | 2021-03-30 | 3 | -0/+18 | |
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| * | equiv: Suggest running async2sync or clk2fflogic where appropriate. | Marcelina Kościelnicka | 2021-03-30 | 2 | -3/+10 | |
| | | | | | See #2713. | |||||
| * | verilog: revise hot comment warnings | Zachary Snow | 2021-03-30 | 1 | -6/+21 | |
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| * | abc9: uniquify blackboxes like whiteboxes (#2695) | Eddie Hung | 2021-03-29 | 2 | -11/+62 | |
| | | | | | | | | | | * abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests | |||||
| * | abc9: fix SCC issues (#2694) | Eddie Hung | 2021-03-29 | 9 | -45/+94 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review | |||||
| * | Bump version | Marcelina Kościelnicka | 2021-03-30 | 1 | -1/+1 | |
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| * | preproc: Fix up conditional handling. | Marcelina Kościelnicka | 2021-03-30 | 1 | -3/+17 | |
| | | | | | | Fixes #2710. Fixes #2711. | |||||
| * | gha: trim macOS dependencies | Zachary Snow | 2021-03-28 | 1 | -3/+1 | |
| | | | | | | | - Only install needed dependencies rather than using Brewfile - Remove brew update (recent enough formulae already baked in) - Saves ~16 minutes in macOS CI | |||||
| * | gha: combine jobs using matrix | Zachary Snow | 2021-03-28 | 1 | -43/+24 | |
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| * | rtlil: add const accessors for modules, wires, and cells | Zachary Snow | 2021-03-25 | 2 | -0/+15 | |
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| * | Merge pull request #2702 from modwizcode/patch-1 | whitequark | 2021-03-24 | 1 | -0/+2 | |
| |\ | | | | | Clarify bugpoint documentation regarding output | |||||
| | * | Clarify bugpoint documentation regarding output | Iris Johnson | 2021-03-24 | 1 | -0/+2 | |
| |/ | | | | | | | Bugpoint's current documentation does specify that the result of a run is stored as the current design, however it's easy to skim over what that means in practice. Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save the reduced design. | |||||
| * | ast: make design available to process_module() | Zachary Snow | 2021-03-24 | 1 | -8/+8 | |
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| * | rtlil: Fix process memwr roundtrip. | Marcelina Kościelnicka | 2021-03-23 | 1 | -1/+1 | |
| | | | | | Fixes #2646 fallout. | |||||
| * | Merge pull request #2696 from nakengelhardt/guidelines | N. Engelhardt | 2021-03-23 | 11 | -318/+295 | |
| |\ | | | | | split CodingReadme into multiple files | |||||
| | * | split CodingReadme into multiple files | N. Engelhardt | 2021-03-22 | 11 | -318/+295 | |
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| * | | quicklogic: Add .gitignore file for test outputs. | Marcelina Kościelnicka | 2021-03-23 | 1 | -0/+4 | |
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| * | | json: Improve the "processes in module" message a bit. | Marcelina Kościelnicka | 2021-03-23 | 1 | -1/+1 | |
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| * | verilog: check entire user type stack for type definition | Xiretza | 2021-03-21 | 2 | -6/+22 | |
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index : iCE40/yosys | |
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