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* Add testcase from removed opt_ff.{v,ys}Eddie Hung2019-08-071-0/+32
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* Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but runEddie Hung2019-08-072-24/+0
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* Allow whitebox modules to be overwrittenEddie Hung2019-08-072-3/+1
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* Update CHANGELOGEddie Hung2019-08-071-0/+2
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* Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-076-10/+128
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* Add testEddie Hung2019-08-071-1/+10
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* Remove ice40_unlutEddie Hung2019-08-072-107/+0
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* Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* Merge pull request #1248 from YosysHQ/eddie/abc9_speedupEddie Hung2019-08-074-40/+48
|\ | | | | abc9: speedup by using using "clean" more efficiently
| * Add commentEddie Hung2019-08-071-2/+3
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| * Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| | | | | | | | This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
| * Add TODOEddie Hung2019-08-071-0/+2
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| * Compute box_lookup just onceEddie Hung2019-08-071-8/+24
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| * Run "clean" on mapped_mod in its own designEddie Hung2019-08-072-24/+10
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| * Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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* Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
|\ | | | | ecp5: Make cells_sim.v consistent with nextpnr
| * ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-075-3/+226
|\ \ | | | | | | wreduce/opt_expr: improve width reduction for $add and $sub cells
| * | Add signed opt_expr testsEddie Hung2019-08-061-0/+50
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| * | Add signed testEddie Hung2019-08-061-0/+26
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| * | Move LSB-trimming functionality from wreduce to opt_exprEddie Hung2019-08-062-23/+26
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| * | Add SigSpec::extract_end() convenience functionEddie Hung2019-08-061-0/+1
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| * | Restore original SigSpec::extract()Eddie Hung2019-08-061-1/+1
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| * | Move LSB tests from wreduce to opt_exprEddie Hung2019-08-062-99/+101
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| * | Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-0656-172/+763
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| * | | Try and fix againEddie Hung2019-07-191-5/+4
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| * | | Add another testEddie Hung2019-07-191-1/+24
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| * | | Do not access beyond boundsEddie Hung2019-07-191-1/+1
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| * | | Add an SigSpec::at(offset, defval) convenience methodEddie Hung2019-07-191-0/+1
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| * | | Wrap A and B in sigmapEddie Hung2019-07-191-2/+2
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| * | | Remove "top" from messageEddie Hung2019-07-191-1/+1
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| * | | Also optimise MSB of $subEddie Hung2019-07-191-3/+3
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| * | | Add one more test with trimming Y_WIDTH of $subEddie Hung2019-07-191-11/+14
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| * | | Be more explicitEddie Hung2019-07-191-6/+29
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| * | | wreduce for $subEddie Hung2019-07-191-0/+23
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| * | | Add tests for sub tooEddie Hung2019-07-191-1/+48
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| * | | Add testEddie Hung2019-07-191-0/+22
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| * | | SigSpec::extract to take negative lengthsEddie Hung2019-07-191-1/+1
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* | | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-072-94/+206
|\ \ \ \ | | | | | | | | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
| * | | | Support explicit FIRRTL properties for better accommodation of ↵Jim Lawson2019-07-312-94/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
| * | | | Merge remote-tracking branch 'upstream/master'Jim Lawson2019-07-3021-32/+164
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| * \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-07-24199-1214/+9423
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* | \ \ \ \ \ Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
|\ \ \ \ \ \ \ | | | | | | | | | | | | | | | | anlogic : Fix alu mapping
| * | | | | | | anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
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* | | | | | | | Merge pull request #1252 from YosysHQ/clifford/fix1231Clifford Wolf2019-08-071-15/+2
|\ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Fix handling of functions/tasks without top-level begin-end block
| * | | | | | | | Fix handling of functions/tasks without top-level begin-end block, fixes #1231Clifford Wolf2019-08-061-15/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Merge pull request #1253 from YosysHQ/clifford/checkClifford Wolf2019-08-073-9/+17
|\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | Be less aggressive with running design->check()
| * | | | | | | | | Be less aggressive with running design->check()Clifford Wolf2019-08-063-9/+17
| |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | Merge pull request #1257 from YosysHQ/clifford/cellcostsClifford Wolf2019-08-073-109/+103
|\ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|_|/ |/| | | | | | | | Redesign of cell cost API
| * | | | | | | | Tweak default gate costs, cleanup "stat -tech cmos"Clifford Wolf2019-08-072-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
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