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* Add simple CI using github actions.Marcelina Kościelnicka2021-03-181-0/+87
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* modtools: fix use-after-free of cell pointers in ModWalkerXiretza2021-03-181-0/+2
| | | | | | | | cell_inputs and cell_outputs retain cell pointers as their keys across invocations of setup(), which may however be invalidated in the meantime (as happens in e.g. passes/opt/share.cc:1432). A later rehash of the dicts (caused by inserting in ModWalker::add_wire()) will cause them to be dereferenced.
* quicklogic: PolarPro 3 supportLofty2021-03-1820-0/+1033
| | | | | | | | Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-182-5/+28
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* Blackbox all whiteboxes after synthesisgatecat2021-03-1716-9/+24
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* bugpoint: add runner optionZachary Snow2021-03-172-6/+20
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* sv: carry over global typedefs from previous filesZachary Snow2021-03-173-2/+65
| | | | | | | This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-172-4/+30
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* blackbox: Include whiteboxed modulesgatecat2021-03-174-4/+19
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace assert in get_reference with more useful error messageLofty2021-03-171-1/+2
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* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-162-4/+37
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* json: Add support for memories.Marcelina Kościelnicka2021-03-152-0/+88
| | | | | | | | | | | | | | Previously, memories were silently discarded by the JSON backend, making round-tripping modules with them crash. Since there are already some users using JSON to implement custom external passes that use memories (and infer width/size from memory ports), let's fix this by just making JSON backend and frontend support memories as first-class objects. Processes are still not supported, and will now cause a hard error. Fixes #1908.
* proc_arst: Add special-casing of clock signal in conditionals.Marcelina Kościelnicka2021-03-152-23/+82
| | | | | | | | | | | | | | | | | The already-existing special case for conditionals on clock has been remade as follows: - now triggered for the last remaining edge trigger after all others have been converted to async reset, not just when there is only one sync rule in the first place - does not require all contained assignments to be constant, as opposed to a reset conditional — merely const-folds the condition In addition, the code has been refactored a bit; as a bonus, the priority order of async resets found is now preserved in resulting sync rule ordering (though this is not yet respected by proc_dff). Fixes #2656.
* opt_clean: Remove init attribute bits together with removed DFFs.Marcelina Kościelnicka2021-03-152-11/+24
| | | | Fixes #2546.
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-152-18/+63
| | | | | | | | | Among other problems, this also fixes equality comparisons between SigSpec by enforcing a canonical form. Also fix another minor issue with possible non-canonical SigSpec. Fixes #2623.
* Merge pull request #2658 from zachjs/parameters-across-fileswhitequark2021-03-143-1/+21
|\ | | | | sv: allow globals in one file to depend on globals in another
| * sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-123-1/+21
|/ | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* Merge pull request #2653 from zachjs/global-parameterwhitequark2021-03-122-0/+18
|\ | | | | verilog: disallow overriding global parameters
| * verilog: disallow overriding global parametersZachary Snow2021-03-112-0/+18
| | | | | | | | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* | Merge pull request #2642 from whitequark/cxxrtl-noproc-fixeswhitequark2021-03-111-17/+29
|\ \ | | | | | | CXXRTL: some -noproc fixes
| * | cxxrtl: don't assert on edge sync rules tied to a constant.whitequark2021-03-071-0/+4
| | | | | | | | | | | | | | | These are commonly the result of tying an async reset to an inactive level.
| * | cxxrtl: allow `always` sync rules in debug_eval.whitequark2021-03-071-17/+25
| | | | | | | | | | | | | | | These can be produced from `always @*` processes, if `-noproc` is used.
* | | Add _pm.h files to GENLIST, fixes vcxsrc targetMiodrag Milanovic2021-03-111-0/+9
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* | Replace assert in xaiger with more useful error messageDan Ravensloft2021-03-101-1/+2
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* | Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
|\ \ | | | | | | Fix param without default log line
| * | Fix param without default log lineZachary Snow2021-03-071-1/+1
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* | | Bump versionMarcelina Kościelnicka2021-03-081-1/+1
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* | | memory_dff: Remove now-useless write port handling.Marcelina Kościelnicka2021-03-086-82/+19
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* | | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-085-29/+94
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* | | Add support for memory writes in processes.Marcelina Kościelnicka2021-03-0816-43/+245
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* | | sim: Avoid a crash on empty cell connection.Marcelina Kościelnicka2021-03-081-1/+1
| | | | | | | | | | | | Fixes #2513.
* | | proc_dff: Fix emitted FF when a register is not assigned in async resetMarcelina Kościelnicka2021-03-082-0/+27
| | | | | | | | | | | | Fixes #2619.
* | | memory_dff: Remove code looking for $mux cells.Marcelina Kościelnicka2021-03-081-56/+12
| | | | | | | | | | | | This job is now performed by `opt_dff`, which runs before this pass.
* | | tests/bram: Do not generate write address collisions.Marcelina Kościelnicka2021-03-081-5/+23
|/ / | | | | | | These have no defined semantics, making the tests non-deterministic.
* | Replace assert in abc9_ops with more useful error messageDan Ravensloft2021-03-071-1/+9
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* | Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-0712-5/+225
|\ \ | | | | | | sv: support for parameters without default values
| * | sv: support for parameters without default valuesZachary Snow2021-03-0212-5/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-073-0/+39
|\ \ \ | | | | | | | | verilog: impose limit on maximum expression width
| * | | verilog: impose limit on maximum expression widthZachary Snow2021-03-043-0/+39
| | | | | | | | | | | | | | | | | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
* | | | sv: fix some edge cases for unbased unsized literalsZachary Snow2021-03-064-1/+70
| | | | | | | | | | | | | | | | | | | | | | | | - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst`
* | | | proc_clean: Fix empty case removal conditions.Marcelina Kościelnicka2021-03-061-10/+21
| |_|/ |/| | | | | | | | Fixes #2639.
* | | Remove a few functions that, in fact, did not exist in the first place.Marcelina Kościelnicka2021-03-062-3/+1
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* | | Replace assert in addModule with more useful error messageDan Ravensloft2021-03-061-1/+2
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* | | Merge pull request #2635 from whitequark/cxxrtl-memrd-async-addrwhitequark2021-03-051-1/+3
|\ \ \ | | | | | | | | cxxrtl: follow aliases to outlines when emitting $memrd.ADDR
| * | | cxxrtl: follow aliases to outlines when emitting $memrd.ADDR.whitequark2021-03-051-1/+3
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* | | Merge pull request #2634 from whitequark/cxxrtl-debug-wire-typeswhitequark2021-03-051-0/+46
|\ \ \ | | | | | | | | cxxrtl: add pass debug flag to show assigned wire types
| * | | cxxrtl: add pass debug flag to show assigned wire types.whitequark2021-03-051-0/+46
| |/ / | | | | | | | | | Refs #2543.
* | | Merge pull request #2633 from whitequark/cxxrtl-no-topwhitequark2021-03-051-1/+1
|\ \ \ | |/ / |/| | cxxrtl: don't crash on empty designs
| * | cxxrtl: don't crash on empty designs.whitequark2021-03-051-1/+1
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* | Update command-reference-manual.texClaire Xen2021-03-041-4/+4
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