| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs | Clifford Wolf | 2020-01-02 | 1 | -4/+25 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #1606 from YosysHQ/eddie/improve_tests | Eddie Hung | 2020-01-01 | 10 | -19/+20 |
| |\ | | | | | Fix a few issues in tests/arch/* | ||||
| | * | Revert insertion of 'reg', leave note behind | Eddie Hung | 2020-01-01 | 1 | -1/+2 |
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| | * | Fix anlogic async flop mapping | Eddie Hung | 2020-01-01 | 1 | -8/+8 |
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| | * | Do not do call equiv_opt when no sim model exists | Eddie Hung | 2019-12-31 | 2 | -4/+4 |
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| | * | Fix warnings | Eddie Hung | 2019-12-31 | 2 | -2/+2 |
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| | * | Call equiv_opt with -multiclock and -assert | Eddie Hung | 2019-12-31 | 5 | -5/+5 |
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| * | | Merge pull request #1605 from YosysHQ/iopad_fix | Miodrag Milanović | 2020-01-01 | 2 | -0/+22 |
| |\ \ | |/ |/| | iopad mapping should take care of existing io buffers | ||||
| | * | Added a test case | Miodrag Milanovic | 2020-01-01 | 1 | -0/+19 |
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| | * | take skip wire bits into account | Miodrag Milanovic | 2020-01-01 | 1 | -0/+3 |
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| * | Grammar | Eddie Hung | 2019-12-30 | 1 | -1/+1 |
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| * | Update timings for Xilinx S7 cells | Eddie Hung | 2019-12-30 | 1 | -15/+35 |
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| * | Merge pull request #1589 from YosysHQ/iopad_default | Miodrag Milanović | 2019-12-30 | 20 | -71/+67 |
| |\ | | | | | Make iopad option default for all xilinx flows | ||||
| | * | Fix new tests | Miodrag Milanovic | 2019-12-28 | 3 | -6/+6 |
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| | * | Merge remote-tracking branch 'origin/master' into iopad_default | Miodrag Milanovic | 2019-12-28 | 20 | -150/+1614 |
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| | * | | Make test without iopads | Miodrag Milanovic | 2019-12-28 | 17 | -51/+51 |
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| | * | | Revert "Fix xilinx tests, when iopads are default" | Miodrag Milanovic | 2019-12-28 | 16 | -40/+40 |
| | | | | | | | | | | | | | This reverts commit 477e43d921d204c6bc6403109fea6506802c948c. | ||||
| | * | | Addressed review comments | Miodrag Milanovic | 2019-12-21 | 2 | -3/+3 |
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| | * | | iopad no op for compatibility with old scripts | Miodrag Milanovic | 2019-12-21 | 1 | -0/+3 |
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| | * | | Fix xilinx tests, when iopads are default | Miodrag Milanovic | 2019-12-21 | 17 | -42/+44 |
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| | * | | Make iopad option default for all xilinx flows | Miodrag Milanovic | 2019-12-21 | 1 | -14/+5 |
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| * | | | Merge pull request #1599 from YosysHQ/eddie/retry_1588 | Eddie Hung | 2019-12-30 | 4 | -20/+87 |
| |\ \ \ | | | | | | | | | Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once" | ||||
| | * | | | Add #1598 testcase | Eddie Hung | 2019-12-27 | 3 | -0/+48 |
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| | * | | | write_xaiger: inherit port ordering from original module | Eddie Hung | 2019-12-27 | 1 | -5/+16 |
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| | * | | | Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup" | Eddie Hung | 2019-12-27 | 1 | -19/+27 |
| | | |/ | |/| | | | | | | | | | | This reverts commit 92654f73ea92ee9e390c8ab50d8cb51c47a7ffa9, reversing changes made to 3e14ff16676884a1f65cf0eeb0ca9cb1958b8804. | ||||
| * | | | Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5 | Eddie Hung | 2019-12-30 | 3 | -14/+6 |
| |\ \ \ | |/ / |/| | | Nitpick cleanup for ecp5 | ||||
| | * | | Update resource count | Eddie Hung | 2019-12-28 | 1 | -3/+3 |
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| | * | | Nitpick cleanup for ecp5 | Eddie Hung | 2019-12-27 | 2 | -11/+3 |
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| * | | Merge branch 'master' of github.com:YosysHQ/yosys | Eddie Hung | 2019-12-27 | 1 | -27/+19 |
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| | * \ | Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup | David Shah | 2019-12-27 | 1 | -27/+19 |
| | |\ \ | | | | | | | | | Revert "write_xaiger: only instantiate each whitebox cell type once" | ||||
| | | * | | Revert "write_xaiger: only instantiate each whitebox cell type once" | David Shah | 2019-12-27 | 1 | -27/+19 |
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| * / / | write_xaiger: simplify c{i,o}_bits | Eddie Hung | 2019-12-27 | 1 | -12/+6 |
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| * | | fixed invalid char | Miodrag Milanovic | 2019-12-25 | 1 | -1/+1 |
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| * | | iopadmap: Emit tristate buffers with const OE for some edge cases. | Marcin Kościelnicki | 2019-12-25 | 2 | -23/+91 |
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| * | | Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen | Marcin Kościelnicki | 2019-12-25 | 12 | -81/+1136 |
| |\ \ | | | | | | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | ||||
| | * | | Minor nit fixes | Marcin Kościelnicki | 2019-12-25 | 1 | -2/+2 |
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| | * | | Add DSP cascade tests | Eddie Hung | 2019-12-23 | 1 | -0/+89 |
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| | * | | Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too | Eddie Hung | 2019-12-23 | 1 | -8/+18 |
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| | * | | Fix CEA/CEB check | Eddie Hung | 2019-12-23 | 1 | -2/+2 |
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| | * | | Fix checking CE[AB] and for direct connections | Eddie Hung | 2019-12-23 | 1 | -18/+40 |
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| | * | | Support unregistered cascades for A and B inputs | Eddie Hung | 2019-12-23 | 1 | -47/+74 |
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| | * | | Add DSP48A* PCOUT -> PCIN cascade support | Eddie Hung | 2019-12-23 | 1 | -10/+10 |
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| | * | | xilinx_dsp: Initial DSP48A/DSP48A1 support. | Marcin Kościelnicki | 2019-12-22 | 10 | -14/+921 |
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| * / | xilinx: Test our DSP48A/DSP48A1 simulation models. | Marcin Kościelnicki | 2019-12-23 | 5 | -7/+362 |
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| * | Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup | Eddie Hung | 2019-12-20 | 1 | -19/+27 |
| |\ | | | | | write_xaiger: only instantiate each whitebox cell type once | ||||
| | * | write_xaiger: only instantiate each whitebox cell type once | Eddie Hung | 2019-12-20 | 1 | -19/+27 |
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| * | | Add abc9_arrival times for RAM{32,64}M | Eddie Hung | 2019-12-20 | 1 | -24/+10 |
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| * | | Add RAM{32,64}M to abc9_map.v | Eddie Hung | 2019-12-20 | 1 | -0/+78 |
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| * | | Put specify/endspecify inside `` | Eddie Hung | 2019-12-20 | 1 | -4/+4 |
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| * | | Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut | Eddie Hung | 2019-12-20 | 1 | -19/+18 |
| |\ \ | |/ |/| | Interpret "abc9 -lut" as lut string only if [0-9:] | ||||
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index : iCE40/yosys | |
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