iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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\| * \| \| \| \| \| \| \|	kernel: Ensure `dict` always hashes to the same value given the same contents.	Alberto Gonzalez	2020-05-14	1	-3/+6
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\| * \| \| \| \| \| \| \|	kernel: Re-implement `dict` hash code as a `dict` member function instead of ↵	Alberto Gonzalez	2020-05-14	1	-20/+14
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	a specialized template for `hash_ops`.
\| * \| \| \| \| \| \| \|	techmap: Replace naughty `const_cast<>()`s.	Alberto Gonzalez	2020-05-14	1	-2/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
\| * \| \| \| \| \| \| \|	techmap: Replace pseudo-private member usage with the range accessor ↵	Alberto Gonzalez	2020-05-14	1	-3/+3
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	function and some naughty `const_cast<>()`s.
\| * \| \| \| \| \| \| \|	techmap: sort celltypeMap as it determines techmap order	Eddie Hung	2020-05-14	1	-1/+5
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\| * \| \| \| \| \| \| \|	Replace `std::set`s using custom comparators with `pool`.	Alberto Gonzalez	2020-05-14	1	-4/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
\| * \| \| \| \| \| \| \|	techmap: prefix special wires with backslash for use as IdString	Eddie Hung	2020-05-14	3	-12/+14
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\| * \| \| \| \| \| \| \|	Further clean up `passes/techmap/techmap.cc`.	Alberto Gonzalez	2020-05-14	1	-5/+6
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
\| * \| \| \| \| \| \| \|	Use `emplace()` for more efficient insertion into various `dict`s.	Alberto Gonzalez	2020-05-14	1	-8/+8
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\| * \| \| \| \| \| \| \|	Build constant bits directly rather than constructing an object and copying ↵	Alberto Gonzalez	2020-05-14	1	-2/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	its bits.
\| * \| \| \| \| \| \| \|	Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.	Alberto Gonzalez	2020-05-14	1	-2/+2
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\| * \| \| \| \| \| \| \|	Use `emplace()` rather than `insert()`.	Alberto Gonzalez	2020-05-14	1	-1/+1
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\| * \| \| \| \| \| \| \|	Clean up pseudo-private member usage and ensure range iteration uses ↵	Alberto Gonzalez	2020-05-14	1	-17/+17
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	references where possible to avoid unnecessary copies.
\| * \| \| \| \| \| \| \|	Clean up extraneous buffer.	Alberto Gonzalez	2020-05-14	1	-5/+2
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\| * \| \| \| \| \| \| \|	Replace `std::map` with `dict` for `unique_bit_id`.	Alberto Gonzalez	2020-05-14	1	-1/+1
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\| * \| \| \| \| \| \| \|	Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵	Alberto Gonzalez	2020-05-14	1	-3/+3
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	`cellbits_to_tplbits`.
\| * \| \| \| \| \| \| \|	Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵	Alberto Gonzalez	2020-05-14	1	-3/+3
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	`outbit_to_cell`.
\| * \| \| \| \| \| \| \|	Replace `std::map` with `dict` for `TechmapWires` type.	Alberto Gonzalez	2020-05-14	1	-1/+1
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\| * \| \| \| \| \| \| \|	Replace `std::map` with `dict` for `celltypeMap`.	Alberto Gonzalez	2020-05-14	1	-3/+3
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\| * \| \| \| \| \| \| \|	Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.	Alberto Gonzalez	2020-05-14	1	-4/+4
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\| * \| \| \| \| \| \| \|	Replace `std::map` with `dict` for `positional_ports`.	Alberto Gonzalez	2020-05-14	1	-1/+1
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\| * \| \| \| \| \| \| \|	Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵	Alberto Gonzalez	2020-05-14	3	-10/+25
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	`std::map` for `techmap_cache` and `techmap_do_cache`.
\| * \| \| \| \| \| \| \|	Replace `std::map` with `dict` for `simplemap_mappers`.	Alberto Gonzalez	2020-05-14	3	-5/+5
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\| * \| \| \| \| \| \| \|	Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.	Alberto Gonzalez	2020-05-14	1	-10/+10
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\| * \| \| \| \| \| \| \|	Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵	Alberto Gonzalez	2020-05-14	1	-21/+21
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	`passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
\| * \| \| \| \| \| \| \|	Do not modify design modules while iterating over `modules()`.	Alberto Gonzalez	2020-05-14	1	-1/+4
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
\| * \| \| \| \| \| \| \|	Clean up pseudo-private member usage, superfluous `std::vector` ↵	Alberto Gonzalez	2020-05-14	1	-76/+70
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
* \| \| \| \| \| \| \| \|	Merge pull request #2081 from YosysHQ/eddie/blackbox_ast	Eddie Hung	2020-05-30	1	-25/+1
\|\ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	blackbox: use Module::makeblackbox() method
\| * \| \| \| \| \| \| \| \|	blackbox: re-use existing Module::makeblackbox() method	Eddie Hung	2020-05-25	1	-25/+1
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* \| \| \| \| \| \| \| \|	Merge pull request #2018 from boqwxp/qbfsat-timeout	clairexen	2020-05-30	3	-18/+84
\|\ \ \ \ \ \ \ \ \ \| \|_\|_\|_\|_\|_\|_\|/ / \|/\| \| \| \| \| \| \| \|	smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
\| * \| \| \| \| \| \| \|	smtbmc: Remove superfluous `yosys-smt2-timeout` file macro.	Alberto Gonzalez	2020-05-29	1	-4/+0
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Co-Authored-By: clairexen <claire@symbioticeda.com>
\| * \| \| \| \| \| \| \|	smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, ↵	Alberto Gonzalez	2020-05-25	3	-18/+88
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	and CVC4.
* \| \| \| \| \| \| \| \|	Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic	clairexen	2020-05-29	3	-2/+11
\|\ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	ast/simplify: don't bitblast async ROMs declared as `logic`
\| * \| \| \| \| \| \| \| \|	ast/simplify: don't bitblast async ROMs declared as `logic`.	whitequark	2020-05-05	3	-2/+11
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fixes #2020.
* \| \| \| \| \| \| \| \| \|	Merge pull request #1885 from Xiretza/mod-rem-cells	clairexen	2020-05-29	26	-40/+540
\|\ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Fix modulo/remainder semantics
\| * \| \| \| \| \| \| \| \| \|	Document division and modulo cells	Xiretza	2020-05-28	1	-0/+23
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\| * \| \| \| \| \| \| \| \| \|	Update CHANGELOG	Xiretza	2020-05-28	1	-0/+1
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\| * \| \| \| \| \| \| \| \| \|	Add comments for mod/div semantics to rtlil.h	Xiretza	2020-05-28	1	-0/+4
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\| * \| \| \| \| \| \| \| \| \|	Expand tests/simple/constmuldivmod.v	Xiretza	2020-05-28	1	-1/+41
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\| * \| \| \| \| \| \| \| \| \|	Add flooring division operator	Xiretza	2020-05-28	19	-24/+213
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
\| * \| \| \| \| \| \| \| \| \|	Add flooring modulo operator	Xiretza	2020-05-28	23	-37/+280
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* \| \| \| \| \| \| \| \| \| \|	Merge pull request #2092 from whitequark/rtlil-no-space-control	clairexen	2020-05-29	2	-6/+11
\|\ \ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Restrict RTLIL::IdString to not contain whitespace or control chars
\| * \| \| \| \| \| \| \| \| \| \|	Restrict RTLIL::IdString to not contain whitespace or control chars.	whitequark	2020-05-29	2	-6/+11
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	This is an existing invariant (most backends can't cope with these) but one that was not checked or documented.
* \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #2017 from boqwxp/qbfsat-cvc4	clairexen	2020-05-29	1	-2/+6
\|\ \ \ \ \ \ \ \ \ \ \ \ \| \| \|_\|_\|/ / / / / / / / \| \|/\| \| \| \| \| \| \| \| \| \|	qbfsat: Add support for CVC4.
\| * \| \| \| \| \| \| \| \| \| \|	qbfsat: Add support for CVC4.	Alberto Gonzalez	2020-05-25	1	-2/+6
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* \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #2016 from boqwxp/qbfsat-yices	clairexen	2020-05-29	2	-21/+52
\|\\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices the default.
\| * \| \| \| \| \| \| \| \| \| \|	qbfsat: Move SMT2 info statements back to the top of the file.	Alberto Gonzalez	2020-05-25	1	-3/+3
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\| * \| \| \| \| \| \| \| \| \| \|	qbfsat: Add `-solver` option and allow choice of Z3 or Yices, making Yices ↵	Alberto Gonzalez	2020-05-25	2	-23/+54
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	the default. Ensures that "BV" is the logic whenever solving an exists-forall problem with Yices, moves the "(set-logic ...)" directive above any non-info line, sets the `ef-max-iters` parameter to a very high number when using Yices in exists-forall mode so as not to prematurely abandon difficult problems, and does not provide the incompatible "--incremental" Yices argument when in exists-forall mode.
* \| \| \| \| \| \| \| \| \| \| \|	Merge pull request #2097 from whitequark/ilang_lexer-fix-erange	whitequark	2020-05-29	1	-1/+3
\|\ \ \ \ \ \ \ \ \ \ \ \ \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	ilang_lexer: fix check for out of range literal
\| * \| \| \| \| \| \| \| \| \| \| \|	ilang_lexer: fix check for out of range literal.	whitequark	2020-05-29	1	-1/+3
\| \| \|_\|/ / / / / / / / / \| \|/\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Commit ca70a104 did not use a correct check.