| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | | | | | | | | Fix check | Eddie Hung | 2019-08-09 | 1 | -4/+6 | |
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| * | | | | | | | | | | | | Revert "Fix typo" | Eddie Hung | 2019-08-09 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e3c39cc450a0317ad7e8234bb866d55465548c9c. | |||||
| * | | | | | | | | | | | | Remove muxY and ffY for now | Eddie Hung | 2019-08-08 | 2 | -35/+33 | |
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| * | | | | | | | | | | | | Remove signed from ports in +/xilinx/dsp_map.v | Eddie Hung | 2019-08-08 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing | Eddie Hung | 2019-08-08 | 6 | -40/+119 | |
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| * | | | | | | | | | | | | Combine techmap calls | Eddie Hung | 2019-08-08 | 1 | -2/+1 | |
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| * | | | | | | | | | | | | Only pack registers if {A,B,P}REG = 0, do not pack $dffe | Eddie Hung | 2019-08-08 | 1 | -3/+6 | |
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| * | | | | | | | | | | | | Move xilinx_dsp to before alumacc | Eddie Hung | 2019-08-08 | 1 | -6/+4 | |
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| * | | | | | | | | | | | | Disable $dffe | Eddie Hung | 2019-08-08 | 1 | -8/+8 | |
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| * | | | | | | | | | | | | INMODE is 5 bits | Eddie Hung | 2019-08-08 | 1 | -1/+1 | |
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| * | | | | | | | | | | | | Fix copy-pasta typo | Eddie Hung | 2019-08-08 | 1 | -2/+2 | |
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| * | | | | | | | | | | | | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinx | David Shah | 2019-08-08 | 1 | -11/+11 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | | | | | | ecp5: Bring up to date with mul2dsp changes | David Shah | 2019-08-08 | 2 | -2/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | David Shah | 2019-08-08 | 52 | -562/+1165 | |
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| | * | | | | | | | | | | | | Fix compile error | Eddie Hung | 2019-08-07 | 1 | -2/+2 | |
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| | * | | | | | | | | | | | | Run "opt_expr -fine" instead of "wreduce" due to #1213 | Eddie Hung | 2019-08-07 | 1 | -2/+1 | |
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| | * | | | | | | | | | | | | Do not SigSpec::extract() beyond bounds | Eddie Hung | 2019-08-07 | 2 | -8/+10 | |
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| | * | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-08-07 | 49 | -552/+1134 | |
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| | | * | | | | | | | | | | | Merge pull request #1248 from YosysHQ/eddie/abc9_speedup | Eddie Hung | 2019-08-07 | 4 | -40/+48 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / / | | |/| | | | | | | | | | | abc9: speedup by using using "clean" more efficiently | |||||
| | | | * | | | | | | | | | | Add comment | Eddie Hung | 2019-08-07 | 1 | -2/+3 | |
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| | | | * | | | | | | | | | | Revert "Add TODO" | Eddie Hung | 2019-08-07 | 1 | -2/+0 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a. | |||||
| | | | * | | | | | | | | | | Add TODO | Eddie Hung | 2019-08-07 | 1 | -0/+2 | |
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| | | | * | | | | | | | | | | Compute box_lookup just once | Eddie Hung | 2019-08-07 | 1 | -8/+24 | |
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| | | | * | | | | | | | | | | Run "clean" on mapped_mod in its own design | Eddie Hung | 2019-08-07 | 2 | -24/+10 | |
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| | | | * | | | | | | | | | | Run "clean -purge" on holes_module in its own design | Eddie Hung | 2019-08-07 | 1 | -6/+11 | |
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| | | * | | | | | | | | | | Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes | David Shah | 2019-08-07 | 1 | -101/+244 | |
| | | |\ \ \ \ \ \ \ \ \ \ | | | |_|/ / / / / / / / | | |/| | | | | | | | | | ecp5: Make cells_sim.v consistent with nextpnr | |||||
| | | | * | | | | | | | | | ecp5: Make cells_sim.v consistent with nextpnr | David Shah | 2019-08-07 | 1 | -101/+244 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| | | * | | | | | | | | | | Merge pull request #1213 from YosysHQ/eddie/wreduce_add | Clifford Wolf | 2019-08-07 | 5 | -3/+226 | |
| | | |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | wreduce/opt_expr: improve width reduction for $add and $sub cells | |||||
| | | | * | | | | | | | | | | Add signed opt_expr tests | Eddie Hung | 2019-08-06 | 1 | -0/+50 | |
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| | | | * | | | | | | | | | | Add signed test | Eddie Hung | 2019-08-06 | 1 | -0/+26 | |
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| | | | * | | | | | | | | | | Move LSB-trimming functionality from wreduce to opt_expr | Eddie Hung | 2019-08-06 | 2 | -23/+26 | |
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| | | | * | | | | | | | | | | Add SigSpec::extract_end() convenience function | Eddie Hung | 2019-08-06 | 1 | -0/+1 | |
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| | | | * | | | | | | | | | | Restore original SigSpec::extract() | Eddie Hung | 2019-08-06 | 1 | -1/+1 | |
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| | | | * | | | | | | | | | | Move LSB tests from wreduce to opt_expr | Eddie Hung | 2019-08-06 | 2 | -99/+101 | |
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| | | | * | | | | | | | | | | Merge remote-tracking branch 'origin/master' into eddie/wreduce_add | Eddie Hung | 2019-08-06 | 56 | -172/+763 | |
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| | | | * | | | | | | | | | | Try and fix again | Eddie Hung | 2019-07-19 | 1 | -5/+4 | |
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| | | * | | | | | | | | | | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor | Clifford Wolf | 2019-08-07 | 2 | -94/+206 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences. | |||||
| | | | * | | | | | | | | | | | Support explicit FIRRTL properties for better accommodation of ↵ | Jim Lawson | 2019-07-31 | 2 | -94/+206 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FIRRTL/Verilog semantic differences. Use FIRRTL spec vlaues for definition of FIRRTL widths. Added support for '$pos`, `$pow` and `$xnor` cells. Enable tests/simple/operators.v since all operators tested there are now supported. Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors. | |||||
| | | | * | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Jim Lawson | 2019-07-30 | 21 | -32/+164 | |
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| | | | * | | | | | | | | | | | Merge remote-tracking branch 'upstream/master' | Jim Lawson | 2019-07-24 | 199 | -1214/+9423 | |
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| | | * | \ \ \ \ \ \ \ \ \ \ \ | Merge pull request #1249 from mmicko/anlogic_fix | Clifford Wolf | 2019-08-07 | 1 | -16/+8 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | anlogic : Fix alu mapping | |||||
| | | | * | | | | | | | | | | | | | anlogic : Fix alu mapping | Miodrag Milanovic | 2019-08-03 | 1 | -16/+8 | |
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| | | * | | | | | | | | | | | | | Merge pull request #1252 from YosysHQ/clifford/fix1231 | Clifford Wolf | 2019-08-07 | 1 | -15/+2 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix handling of functions/tasks without top-level begin-end block | |||||
| | | | * | | | | | | | | | | | | | Fix handling of functions/tasks without top-level begin-end block, fixes #1231 | Clifford Wolf | 2019-08-06 | 1 | -15/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | | | | | | | | Merge pull request #1253 from YosysHQ/clifford/check | Clifford Wolf | 2019-08-07 | 3 | -9/+17 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Be less aggressive with running design->check() | |||||
| | | | * | | | | | | | | | | | | | | Be less aggressive with running design->check() | Clifford Wolf | 2019-08-06 | 3 | -9/+17 | |
| | | | |/ / / / / / / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | | | | | | | | Merge pull request #1257 from YosysHQ/clifford/cellcosts | Clifford Wolf | 2019-08-07 | 3 | -109/+103 | |
| | | |\ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|/ / / / / / | | |/| | | | | | | | | | | | | | Redesign of cell cost API | |||||
| | | | * | | | | | | | | | | | | | Tweak default gate costs, cleanup "stat -tech cmos" | Clifford Wolf | 2019-08-07 | 2 | -20/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | | * | | | | | | | | | | | | | Redesign of cell cost API | Clifford Wolf | 2019-08-07 | 2 | -93/+97 | |
| | | | | |_|_|_|_|_|/ / / / / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | | | | | | | | Update CHANGELOG | David Shah | 2019-08-07 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
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index : iCE40/yosys | |
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