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| * | | | | | | | | | | | | | | | undo formatting fuckupPepijn de Vos2019-10-281-25/+25
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| * | | | | | | | | | | | | | | | add wide lutsPepijn de Vos2019-10-283-36/+119
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| * | | | | | | | | | | | | | | | add 32-bit BRAM and byte-enablesPepijn de Vos2019-10-282-4/+25
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| * | | | | | | | | | | | | | | | ALU sim tweaksPepijn de Vos2019-10-242-13/+13
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| * | | | | | | | | | | | | | | | Add some testsPepijn de Vos2019-10-2110-0/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram
| * | | | | | | | | | | | | | | | add a few more missing dffPepijn de Vos2019-10-211-7/+16
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| * | | | | | | | | | | | | | | | add negedge DFFPepijn de Vos2019-10-212-15/+139
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| * | | | | | | | | | | | | | | | use ADDSUB ALU mode to remove invertersPepijn de Vos2019-10-212-7/+77
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| * | | | | | | | | | | | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-10-21275-2678/+32872
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| * | | | | | | | | | | | | | | | | remove duplicate DFFRPepijn de Vos2019-10-161-10/+0
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| * | | | | | | | | | | | | | | | | Revert "add MUX support"Pepijn de Vos2019-09-063-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990.
| * | | | | | | | | | | | | | | | | fix BRAM width and initPepijn de Vos2019-09-062-12/+28
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| * | | | | | | | | | | | | | | | | add more DFF to sim libPepijn de Vos2019-09-062-6/+111
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| * | | | | | | | | | | | | | | | | WIP aditional DFF primitivesPepijn de Vos2019-09-052-1/+48
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| * | | | | | | | | | | | | | | | | support bram initialisationPepijn de Vos2019-09-055-3/+25
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| * | | | | | | | | | | | | | | | | use singleton ground and vcc nets, apparently this makes pnr happierPepijn de Vos2019-09-051-1/+1
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| * | | | | | | | | | | | | | | | | add MUX supportPepijn de Vos2019-09-053-0/+17
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| * | | | | | | | | | | | | | | | | set undriven pads to zeroPepijn de Vos2019-09-042-2/+3
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| * | | | | | | | | | | | | | | | | fix tcl scriptPepijn de Vos2019-09-041-2/+1
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| * | | | | | | | | | | | | | | | | add broken TCL run scriptPepijn de Vos2019-09-042-0/+18
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| * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'diego/gowin'Pepijn de Vos2019-09-042-2/+2
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| | * | | | | | | | | | | | | | | | | Updating gowinDiego H2019-09-022-2/+2
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| * | | | | | | | | | | | | | | | | | Add demonstration of breakagePepijn de Vos2019-09-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unused outputs lead to undriven buffers, which lead to syntax errors.
| * | | | | | | | | | | | | | | | | | Update example for GW1NR-9Pepijn de Vos2019-09-044-47/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the Trenz TEC0117 on Gowin IDE 1.8.4
| * | | | | | | | | | | | | | | | | | Merge branch 'master' of https://github.com/YosysHQ/yosysPepijn de Vos2019-09-043-5/+6
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| * | | | | | | | | | | | | | | | | | | gowin: add splitnets to appease the PnRPepijn de Vos2019-09-041-0/+1
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* | | | | | | | | | | | | | | | | | | | Fix #1462, #1480.Marcin Kościelnicki2019-11-194-9/+40
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* | | | | | | | | | | | | | | | | | | | xilinx: Add simulation models for MULT18X18* and DSP48A*.Marcin Kościelnicki2019-11-193-132/+516
| |_|_|_|_|_|/ / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)
* | | | | | | | | | | | | | | | | | | Merge pull request #1497 from YosysHQ/mwk/extract-fa-fixClifford Wolf2019-11-182-4/+21
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix #1496.
| * | | | | | | | | | | | | | | | | | | Fix #1496.Marcin Kościelnicki2019-11-182-4/+21
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* | | | | | | | | | | | | | | | | | | | Merge pull request #1494 from whitequark/write_verilog-extmemwhitequark2019-11-181-10/+80
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | write_verilog: add -extmem option, to write split memory init files
| * | | | | | | | | | | | | | | | | | | write_verilog: add -extmem option, to write split memory init files.whitequark2019-11-181-10/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used.
* | | | | | | | | | | | | | | | | | | | Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arstClifford Wolf2019-11-171-4/+10
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|_|_|/ / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | wreduce: Don't trim zeros or sext when not matching ARST_VALUE
| * | | | | | | | | | | | | | | | | | | wreduce: Don't trim zeros or sext when not matching ARST_VALUEDavid Shah2019-11-141-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | | ecp5: Use new autoname pass for better cell/net namesDavid Shah2019-11-151-0/+1
| |/ / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-143-0/+136
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |/ / / / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | Add "autoname" pass and use it in "synth_ice40"
| * | | | | | | | | | | | | | | | | | Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-133-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | | | | | | | | | Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streamsClifford Wolf2019-11-141-6/+286
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Python Wrappers: Expose global variables and allow logging to python streams
| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosys into ↵Benedikt Tutzer2019-10-1525-61/+345
| |\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | feature/python_wrappers/globals_and_streams
| * | | | | | | | | | | | | | | | | | | | Fix renaming all classes to Cpp*Benedikt Tutzer2019-10-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (This is only relevant for classes that are exposed twice, one time as a base class and one time as a derived class that can in turn be overridden in python, but actually all others were renamed)
| * | | | | | | | | | | | | | | | | | | | Expose global variables and allow logging to python streamsBenedikt Tutzer2019-10-091-6/+286
| | |_|_|_|_|_|_|_|_|_|_|_|_|_|_|_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Global variables are now accessible via the Yosys class. To capture Yosys output, once can now register an output stream in Pyosys.
* | | | | | | | | | | | | | | | | | | | Merge pull request #1465 from YosysHQ/dave/ice40_timing_simClifford Wolf2019-11-141-14/+436
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ice40: Support for post-place-and-route timing simulations
| * | | | | | | | | | | | | | | | | | | | ice40: Add post-pnr ICESTORM_RAM model and fix FFsDavid Shah2019-10-231-2/+340
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | | | | | | | | | | | | | | | | | | | ice40: Support for post-pnr timing simulationDavid Shah2019-10-231-12/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | | | | | | | | | | | | | | Merge branch 'makaimann-label-bads-btor'Clifford Wolf2019-11-141-1/+6
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| * | | | | | | | | | | | | | | | | | | | | Use cell name for btor bad state props when it is a public nameClifford Wolf2019-11-141-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | | | | | | | | | | | | Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into ↵Clifford Wolf2019-11-141-1/+10
|/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | makaimann-label-bads-btor
| * | | | | | | | | | | | | | | | | | | | | Add an info string symbol for bad states in btor backendMakai Mann2019-11-111-1/+10
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* | | | | | | | | | | | | | | | | | | | | Merge pull request #1488 from whitequark/flowmap-fixeswhitequark2019-11-131-2/+3
|\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|/ / / / / / / / / / / / / / / / |/| | | | | | | | | | | | | | | | | | | | flowmap: fix a few crashes
| * | | | | | | | | | | | | | | | | | | | flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes #1475.
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