aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * write_verilog: dump zero width sigspecs correctly.whitequark2021-12-111-1/+2
|/ | | | | | | | | | | | | Before this commit, zero width sigspecs were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) PR #1203 has addressed this issue before, but in an incomplete way.
* Bump versiongithub-actions[bot]2021-12-111-1/+1
|
* Merge pull request #3102 from YosysHQ/claire/enumxzMiodrag Milanović2021-12-101-1/+1
|\ | | | | Fix verific import of enum values with x and/or z
| * Fix verific import of enum values with x and/or zClaire Xenia Wolf2021-12-101-1/+1
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Merge pull request #3097 from YosysHQ/modportMiodrag Milanović2021-12-101-2/+12
|\ \ | |/ |/| If direction NONE use that from first bit
| * Update verific.ccClaire Xen2021-12-101-4/+7
| | | | | | Ad-hoc fixes/improvements
| * If direction NONE use that from first bitMiodrag Milanovic2021-12-081-0/+7
| |
* | Merge pull request #3099 from YosysHQ/claire/readargsClaire Xen2021-12-109-41/+52
|\ \ | | | | | | Use "read" command to parse HDL files from Yosys command-line
| * | Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * | Added "yosys -r <topmodule>"Claire Xenia Wolf2021-12-103-28/+35
| | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * | Use "read" command to parse HDL files from Yosys command-lineClaire Xenia Wolf2021-12-091-4/+8
|/ / | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Bump versiongithub-actions[bot]2021-12-091-1/+1
| |
* | opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-092-12/+2
|/ | | | This is a fixed version of #3072.
* Bump versiongithub-actions[bot]2021-12-041-1/+1
|
* Next dev cycleMiodrag Milanovic2021-12-032-2/+5
|
* Release version 0.12Miodrag Milanovic2021-12-032-3/+3
|
* Update manualMiodrag Milanovic2021-12-031-22/+181
|
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
|
* Make sure cell names are unique for wide operatorsMiodrag Milanovic2021-12-031-2/+2
|
* Bump versiongithub-actions[bot]2021-12-021-1/+1
|
* Update CHANGELOG and CODEOWNERSMiodrag Milanovic2021-12-012-0/+22
|
* Bump versiongithub-actions[bot]2021-11-261-1/+1
|
* intel_alm: preliminary Arria V supportLofty2021-11-256-7/+199
|
* sta: very crude static timing analysis passLofty2021-11-259-62/+502
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Bump versiongithub-actions[bot]2021-11-181-1/+1
|
* Merge pull request #3080 from YosysHQ/micko/init_wireMiodrag Milanović2021-11-171-4/+6
|\ | | | | Give initial wire unique ID, fixes #2914
| * Give initial wire unique ID, fixes #2914Miodrag Milanovic2021-11-171-4/+6
|/
* Bump versiongithub-actions[bot]2021-11-171-1/+1
|
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-162-7/+74
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Bump versiongithub-actions[bot]2021-11-141-1/+1
|
* synth_gatemate Revert cascade A/B port mixupPatrick Urban2021-11-132-12/+4
|
* synth_gatemate: Remove iob_map invokationPatrick Urban2021-11-131-1/+0
|
* synth_gatemate: Add block RAM cascade supportPatrick Urban2021-11-132-112/+96
| | | | | * add simulation model for block RAM cascade in 40K mode * limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations)
* synth_gatemate: Remove obsolete iob_mapPatrick Urban2021-11-133-61/+2
|
* synth_gatemate: Update passPatrick Urban2021-11-132-69/+33
| | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style
* synth_gatemate: Remove specify blocksPatrick Urban2021-11-131-92/+0
|
* synth_gatemate: Remove gatemate_bramopt passPatrick Urban2021-11-133-148/+0
|
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
|
* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
|
* synth_gatemate: Revise block RAM read modes and initializationPatrick Urban2021-11-133-71/+230
| | | | | | | | * enable mixed read-width / write-width ports in SDP mode * fix NO_CHANGE and WRITE_THROUGH behavior during read access * remove redundant zero-initialization * set A/B_WE bit during map (gatemate_bramopt pass could be removed later) * differentiate "upper" and "lower" initialization for cascade mode
* synth_gatemate: Remove unsupported FF initializationPatrick Urban2021-11-131-2/+0
|
* synth_gatemate: Rename multiplier factor parametersPatrick Urban2021-11-131-13/+10
|
* synth_gatemate: Registers are uninitializedPatrick Urban2021-11-132-3/+3
|
* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
| | | | Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
* synth_gatemate: Apply review remarksPatrick Urban2021-11-136-279/+212
| | | | | | | | * remove unused techmap models in `map_regs.v` * replace RAM initilization loops with 320-bit-writes * add script to test targets in top-level Makefile * remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v` * iterate over all modules in `gatemate_bramopt` pass
* synth_gatemate: Apply review remarksPatrick Urban2021-11-135-141/+86
|
* synth_gatemate: Initial implementationPatrick Urban2021-11-1329-0/+4053
| | | | Signed-off-by: Patrick Urban <patrick.urban@web.de>
* Bump versiongithub-actions[bot]2021-11-131-1/+1
|
* show: Fix wire bit indexing.Marcelina Kościelnicka2021-11-121-3/+16
| | | | Fixes #3078.
* update abcMiodrag Milanovic2021-11-121-1/+1
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-14 16:04:56 +0000