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* | Remove some very strange whitespace in btor.cc (by Larry Doolittle)Clifford Wolf2015-08-051-7/+7
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* | Bugfix in SMV back-end for partially unassigned wiresClifford Wolf2015-08-051-4/+16
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* | Added ENABLE_LIBYOSYS Makefile optionClifford Wolf2015-08-042-14/+10
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* | Added $assert support to SMV back-endClifford Wolf2015-08-041-4/+21
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* | Added libyosys.so buildClifford Wolf2015-08-043-3/+24
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* | Merge pull request #68 from zeldin/masterClifford Wolf2015-08-011-1/+8
|\ \ | | | | | | Add -noautowire option to verilog frontend
| * | Add -noautowire option to verilog frontendMarcus Comstedt2015-08-011-1/+8
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* | Added WORDS parameter to $meminitClifford Wolf2015-07-316-16/+95
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* | Fixed flatten $meminit handlingClifford Wolf2015-07-301-1/+1
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* | Improvements in BLIF back-endClifford Wolf2015-07-291-5/+84
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* | Fixed nested mem2regClifford Wolf2015-07-292-4/+11
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* | Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-271-1/+0
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* | Fixed "check" command for inout portsClifford Wolf2015-07-271-3/+11
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* | Some cleanups in opt_rmdffClifford Wolf2015-07-251-16/+9
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* | Added "miter -assert"Clifford Wolf2015-07-251-1/+93
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* | Keep modules with $assume (like $assert)Clifford Wolf2015-07-251-1/+1
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* | Improved $adff simplificationClifford Wolf2015-07-241-1/+1
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* | iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-201-20/+43
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* | Fixed techmap processes error msgClifford Wolf2015-07-181-2/+3
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* | Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-181-0/+2
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* | Some fixes in "select" commandClifford Wolf2015-07-161-1/+3
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* | Fixed YosysJS.create_worker() usage of this.url_prefixClifford Wolf2015-07-101-1/+1
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* | Improved liberty file test caseClifford Wolf2015-07-061-1/+2
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* | Updated ABCClifford Wolf2015-07-061-1/+1
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* | Do not collect disabled $memwr cellsClifford Wolf2015-07-061-15/+18
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* | Improved YosysJS WebWorker APIClifford Wolf2015-07-043-10/+51
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* | Bugfix in fsm_extractClifford Wolf2015-07-031-3/+16
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* | Added "synth -nofsm"Clifford Wolf2015-07-021-1/+10
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* | Fixed trailing whitespacesClifford Wolf2015-07-02195-729/+729
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* | Added opt_const -clkinvClifford Wolf2015-07-012-6/+95
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* | Added logic-loop error handling to freduceClifford Wolf2015-06-301-0/+11
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* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-06-303-33/+145
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| * | Added YosysJS.create_worker()Clifford Wolf2015-06-283-33/+145
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* | | Bugfix in chparamClifford Wolf2015-06-301-6/+5
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* | | Added design->rename(module, new_name)Clifford Wolf2015-06-303-3/+9
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* | iCE40: set min bram efficiency to 2%Clifford Wolf2015-06-201-2/+2
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* | Using static mem size of 128 MB in emcc buildClifford Wolf2015-06-201-1/+1
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* | Added init support to SMV back-endClifford Wolf2015-06-191-1/+3
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* | Progress in SMV back-endClifford Wolf2015-06-191-64/+115
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* | Progress in SMV back-endClifford Wolf2015-06-192-14/+60
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* | Progress in SMV back-endClifford Wolf2015-06-184-24/+147
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* | Progress in SMV back-endClifford Wolf2015-06-171-11/+72
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* | Added "rename -top new_name"Clifford Wolf2015-06-173-0/+43
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* | Progress in SMV back-endClifford Wolf2015-06-171-11/+64
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* | Progress in SMV back-endClifford Wolf2015-06-161-3/+46
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* | Added "synth -nordff -noalumacc"Clifford Wolf2015-06-151-3/+20
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* | Progress in SMV back-endClifford Wolf2015-06-151-2/+95
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* | Progress in SMV back-endClifford Wolf2015-06-151-7/+85
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* | Added "write_smv" skeletonClifford Wolf2015-06-153-2/+265
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* | Removed debug code from write_smt2Clifford Wolf2015-06-141-2/+0
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