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* Bump versionYosys Bot2020-09-181-1/+1
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* Merge pull request #2329 from antmicro/arrays-fix-multirange-sizeclairexen2020-09-172-2/+27
|\ | | | | Rewrite multirange arrays sizes [n] as [n-1:0]
| * Test multirange (unpacked) arrays sizeLukasz Dalek2020-08-031-0/+16
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Merge pull request #2330 from antmicro/arrays-fix-multirange-accessclairexen2020-09-172-1/+13
|\ \ | | | | | | Fix unsupported subarray access detection
| * | Add test for subarray access on multidimensional arraysLukasz Dalek2020-08-031-0/+12
| | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | Fix subarray access conditionLukasz Dalek2020-08-031-1/+1
| |/ | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Bump versionYosys Bot2020-09-111-1/+1
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* | Merge pull request #2369 from Xiretza/gitignoresMiodrag Milanović2020-09-103-2/+4
|\ \ | | | | | | Add missing gitignores for test artifacts
| * | Add missing gitignores for test artifactsXiretza2020-08-313-2/+4
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* | | Bump versionYosys Bot2020-09-041-1/+1
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* | | Merge pull request #2371 from whitequark/cxxrtl-debug-infowhitequark2020-09-033-30/+177
|\ \ \ | | | | | | | | cxxrtl: expose port direction and driver kind in debug information
| * | | cxxrtl: expose driver kind in debug information.whitequark2020-09-023-12/+112
| | | | | | | | | | | | | | | | | | | | | | | | This can be useful to determine whether the wire should be a part of a design checkpoint, whether it can be used to override design state, and whether driving it may cause a conflict.
| * | | cxxrtl: improve handling of FFs with async inputs (other than CLK).whitequark2020-09-021-22/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, the meaning of "sync def" included some flip-flop cells but not others. There was no actual reason for this; it was just poorly defined. After this commit, a "sync def" means that a wire holds design state because it is connected directly to a flip-flop output, and may never be unbuffered. This is not affected by presence of async inputs.
| * | | cxxrtl: expose port direction in debug information.whitequark2020-09-023-5/+51
| | | | | | | | | | | | | | | | | | | | | | | | This can be useful to distinguish e.g. a combinatorially driven wire with type `CXXRTL_VALUE` from a module input with the same type, as well as general introspection.
| * | | cxxrtl: fix typo in comment. NFC.whitequark2020-09-021-1/+1
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| * | | cxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC.whitequark2020-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | Nodes driven by a constant value have type CXXRTL_VALUE and their `next` pointer set to NULL. (This is already documented.)
* | | | Bump versionYosys Bot2020-09-031-1/+1
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* | | Use latest verificMiodrag Milanovic2020-09-021-1/+1
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* | | Bump versionYosys Bot2020-09-021-1/+1
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* | | Merge pull request #2352 from zachjs/const-func-localparamclairexen2020-09-012-3/+18
|\ \ \ | | | | | | | | Allow localparams in constant functions
| * | | Allow localparams in constant functionsZachary Snow2020-08-202-3/+18
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* | | | Merge pull request #2366 from zachjs/library-formatclairexen2020-09-011-0/+11
|\ \ \ \ | | | | | | | | | | Simple support for %l format specifier
| * | | | Simple support for %l format specifierZachary Snow2020-08-291-0/+11
| |/ / / | | | | | | | | | | | | | | | | Yosys doesn't support libraries, so this provides the same behavior as %m, as some other tools have opted to do.
* | | | Merge pull request #2353 from zachjs/top-scopeclairexen2020-09-012-0/+23
|\ \ \ \ | | | | | | | | | | Module name scope support
| * | | | Module name scope supportZachary Snow2020-08-202-0/+23
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* | | | Merge pull request #2365 from zachjs/const-arg-loop-split-typeclairexen2020-09-012-3/+24
|\ \ \ \ | | | | | | | | | | Fix constant args used with function ports split across declarations
| * | | | Fix constant args used with function ports split across declarationsZachary Snow2020-08-292-3/+24
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* | / / Bump versionYosys Bot2020-09-011-1/+1
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* | | Reorder to prevent crashMiodrag Milanovic2020-08-311-3/+3
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* | | Merge pull request #2368 from YosysHQ/verific_portrangeclairexen2020-08-311-11/+20
|\ \ \ | | | | | | | | Fix import of VHDL enums
| * | | ast recognize lower case x and z and verific gives upper caseMiodrag Milanovic2020-08-301-2/+6
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| * | | Do not check for 1 and 0 onlyMiodrag Milanovic2020-08-301-6/+0
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| * | | Fix import of VHDL enumsMiodrag Milanovic2020-08-301-11/+22
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* | | Bump versionYosys Bot2020-08-301-1/+1
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* | | write_smt2: fix SMT-LIB tutorial URLwhitequark2020-08-291-1/+1
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* | | Bump versionYosys Bot2020-08-291-1/+1
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* | | intel_alm: better map wide but shallow multipliesDan Ravensloft2020-08-281-2/+6
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* | | Bump versionYosys Bot2020-08-281-1/+1
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* | | Merge pull request #2364 from whitequark/manual-typoMiodrag Milanović2020-08-271-1/+1
|\ \ \ | | | | | | | | manual: fix typo
| * | | manual: fix typo.whitequark2020-08-271-1/+1
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* | | Merge pull request #2357 from whitequark/cxxflags-MPwhitequark2020-08-271-1/+1
|\ \ \ | | | | | | | | Add -MP to CXXFLAGS
| * | | Add -MP to CXXFLAGS.whitequark2020-08-261-1/+1
| | | | | | | | | | | | | | | | | | | | This avoids an issue where deleting or moving headers breaks the next incremental build until the outdated *.d files are deleted.
* | | | Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmapwhitequark2020-08-273-9/+17
|\ \ \ \ | | | | | | | | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap
| * | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-263-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* | | | | Merge pull request #2358 from whitequark/rename-ilang-to-rtlilwhitequark2020-08-2728-178/+206
|\ \ \ \ \ | | | | | | | | | | | | Replace "ILANG" with "RTLIL" everywhere
| * | | | | Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-2628-178/+206
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* | | | | dfflegalize: Fix decision tree for adffe.Marcelina Kościelnicka2020-08-271-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an adffe is being legalized, and is not natively supported, prioritize unmapping to adff over converting to dffsre if dffsre is not natively supported itself. Fixes #2361.
* | | | | Bump versionYosys Bot2020-08-271-1/+1
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* | | | | intel_alm: Add multiply signedness to cellsDan Ravensloft2020-08-267-16/+147
|/ / / / | | | | | | | | | | | | | | | | | | | | Quartus assumes unsigned multiplication by default, breaking signed multiplies, so add an input signedness parameter to the MISTRAL_MUL* cells to propagate to Quartus' <family>_mac cells.
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