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* Add missing .gitignoreClifford Wolf2018-12-061-0/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Bugfix in opt_expr handling of a<0 and a>=0Clifford Wolf2018-12-061-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Verific updatesClifford Wolf2018-12-062-54/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #709 from smunaut/issue_708Clifford Wolf2018-12-051-1/+1
|\ | | | | Make return value of $clog2 signed
| * Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | | | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #718 from whitequark/gate2lutClifford Wolf2018-12-0512-4/+151
|\ \ | | | | | | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
| * | synth_ice40: add -noabc option, to use built-in LUT techmapping.whitequark2018-12-051-2/+16
| | | | | | | | | | | | This should be combined with -relut to get sensible results.
| * | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-0510-0/+133
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| * | Fix typo.whitequark2018-12-051-2/+2
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* | Merge pull request #713 from Diego-HR/masterClifford Wolf2018-12-055-12/+91
|\ \ | | | | | | Changes in GoWin synth commands and ALU primitive support
| * | Changes in GoWin synth commands and ALU primitive supportDiego H2018-12-035-12/+91
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* | | Merge pull request #712 from mmicko/anlogic-supportClifford Wolf2018-12-057-0/+1278
|\ \ \ | | | | | | | | Initial support for Anlogic FPGA
| * | | Leave only real black box cellsMiodrag Milanovic2018-12-021-312/+0
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| * | | Initial support for Anlogic FPGAMiodrag Milanovic2018-12-017-0/+1590
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* | | Rename opt_lut.cpp to opt_lut.ccClifford Wolf2018-12-051-0/+0
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #717 from whitequark/opt_lutClifford Wolf2018-12-059-2/+537
|\ \ \ | | | | | | | | Add a new opt_lut pass, which combines inefficiently packed LUTs
| * | | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-053-20/+166
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| * | | opt_lut: always prefer to eliminate 1-LUTs.whitequark2018-12-051-19/+41
| | | | | | | | | | | | | | | | | | | | These are always either buffers or inverters, and keeping the larger LUT preserves more source-level information about the design.
| * | | opt_lut: collect and display statistics.whitequark2018-12-051-4/+33
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| * | | opt_lut: refactor to use a worker. NFC.whitequark2018-12-051-170/+177
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| * | | synth_ice40: add -relut option, to run ice40_unlut and opt_lut.whitequark2018-12-051-1/+13
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| * | | opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-058-1/+320
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* | | | Merge pull request #716 from whitequark/ice40_unlutClifford Wolf2018-12-053-13/+109
|\| | | | | | | | | | | Extract ice40_unlut pass from ice40_opt
| * | | Extract ice40_unlut pass from ice40_opt.whitequark2018-12-053-13/+109
|/ / / | | | | | | | | | | | | | | | | | | | | | Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert them back to logic immediately. This is not desirable if the goal is to operate on $lut cells. If this is desirable, the same result as `ice40_opt -unlut` can be achieved by running simplemap and opt after ice40_unlut.
* | | Merge pull request #719 from YosysHQ/q3k/flailing-around-trying-to-fix-osxSerge Bazanski2018-12-052-3/+2
|\ \ \ | | | | | | | | Fix Travis on OSX
| * | | travis/osx: fix, use clang instead of gccSergiusz Bazanski2018-12-052-3/+2
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* | | Fix typoClifford Wolf2018-12-041-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge pull request #702 from smunaut/min_ce_useClifford Wolf2018-12-042-1/+50
|\ \ \ | |/ / |/| | Add option to only use DFFE is the resulting E signal would be use > N times
| * | ice40: Add option to only use CE if it'd be use by more than X FFsSylvain Munaut2018-11-271-0/+14
| | | | | | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | dff2dffe: Add option for unmap to only remove DFFE with low CE signal useSylvain Munaut2018-11-271-1/+36
| |/ | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #676 from rafaeltp/masterClifford Wolf2018-12-011-10/+17
|\ \ | | | | | | Splits SigSpec into bits before calling check_signal_in_fanout (solves #675)
| * | using [i] to access individual bits of SigSpec and merging bits into a tmp ↵rafaeltp2018-10-211-11/+12
| | | | | | | | | | | | Sig before setting the port to new signal
| * | cleaning up for PRrafaeltp2018-10-202-6/+2
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| * | fixing code stylerafaeltp2018-10-201-1/+1
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| * | solves #675rafaeltp2018-10-202-11/+21
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| * | Merge pull request #1 from YosysHQ/masterrafaeltp2018-10-2020-89/+869
| |\ \ | | | | | | | | updating
* | | | Improve ConstEval error handling for non-eval cell typesClifford Wolf2018-11-292-9/+19
| |_|/ |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add iteration limit to "opt_muxtree"Clifford Wolf2018-11-201-1/+17
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Update ABC to git rev 2ddc57dClifford Wolf2018-11-131-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "write_aiger -I -O -B"Clifford Wolf2018-11-121-2/+36
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-11-124-1/+1044
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| * \ \ Merge pull request #697 from eddiehung/xilinx_ps7Clifford Wolf2018-11-122-0/+624
| |\ \ \ | | | | | | | | | | Add support for PS7 block for Xilinx
| | * | | Add support for Xilinx PS7 blockEddie Hung2018-11-102-0/+624
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| * | | | Merge pull request #695 from daveshah1/ecp5_bbClifford Wolf2018-11-122-1/+420
| |\ \ \ \ | | |/ / / | |/| | | ecp5: Adding some blackbox cells
| | * | | ecp5: Add 'fake' DCU parametersDavid Shah2018-11-091-0/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | ecp5: Add blackboxes for ancillary DCU cellsDavid Shah2018-11-091-0/+18
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | ecp5: Adding some blackbox cellsDavid Shah2018-11-072-1/+391
| | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | Update ABC to git rev 68da3cfClifford Wolf2018-11-111-1/+1
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Set Verific flag vhdl_support_variable_slice=1Clifford Wolf2018-11-091-0/+1
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #696 from arjenroodselaar/verific_darwinClifford Wolf2018-11-091-0/+4
|\ \ \ \ | | | | | | | | | | Use appropriate static libraries when building with Verific on MacOS
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