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* memory_dff: Use Mem helper.Marcelina Kościelnicka2021-05-211-19/+26
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* Run VS build on PRs and each pushMiodrag Milanović2021-05-201-4/+1
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* Bump versionMarcelina Kościelnicka2021-05-201-1/+1
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* tests/blif: Add missing gitignoreMarcelina Kościelnicka2021-05-201-0/+1
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* Visual Studio build actionMiodrag Milanovic2021-05-171-0/+40
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* intel_alm: Fix illegal carry chainsgatecat2021-05-154-7/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add global buffer insertiongatecat2021-05-1519-45/+119
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* intel_alm: Add IO buffer insertiongatecat2021-05-1519-46/+166
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Change the type of current_module to ModuleRupert Swarbrick2021-05-132-24/+26
| | | | | | | | | | | The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support.
* Use range-based for loop in AST::processRupert Swarbrick2021-05-131-21/+21
| | | | | | No functional change: just get rid of the explicit iterator and replace (*it)-> with child->. It's even the same number of characters, but is hopefully a little easier to read.
* Add missing parameters for MULT18X18D and ALU54B to ECP5 techlib.Adam Greig2021-05-121-0/+22
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* sv: check validity of package end labelZachary Snow2021-05-102-0/+17
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* blif: Use library cells' start_offset and upto for wideports.Marcelina Kościelnicka2021-05-084-10/+54
| | | | Fixes #2729.
* connect: Add -assert option, fix non-working sigmap.Marcelina Kościelnicka2021-05-081-4/+24
| | | | Should be useful for writing tests.
* opt_dff: Fix NOT gates wired in reverse.Marcelina Kościelnicka2021-05-042-10/+15
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* Merge pull request #2738 from mdko/xilinx-blifMiodrag Milanović2021-04-271-1/+1
|\ | | | | Fix use of blif name in synth_xilinx command
| * Fix use of blif name in synth_xilinx commandMichael Christensen2021-04-271-1/+1
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* Merge pull request #2737 from YosysHQ/claire/fix2736Claire Xen2021-04-261-0/+4
|\ | | | | Remove duplicates from conns array in JSON front-end, fixes #2736
| * Remove duplicates from conns array in JSON front-end, fixes #2736Claire Xenia Wolf2021-04-261-0/+4
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* Merge pull request #2669 from YosysHQ/claire/ice40defaultsClaire Xen2021-04-212-26/+62
|\ | | | | Add input default assignments to iCE40 cell library
| * Add default assignments to other SB_* simulation modelsClaire Xenia Wolf2021-04-201-24/+44
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-202-2/+18
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* quicklogic: ABC9 synthesisLofty2021-04-1712-22/+97
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* sf2: fix name of AND modulesStefan Riesenberger2021-04-091-3/+3
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* Merge pull request #2724 from whitequark/flatten-rewrite-memwr-memidwhitequark2021-04-091-0/+3
|\ | | | | flatten: rewrite memid in memwr actions
| * flatten: rewrite memid in memwr actions.whitequark2021-04-091-0/+3
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* preproc: test coverage for #2712Zachary Snow2021-03-303-0/+18
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* equiv: Suggest running async2sync or clk2fflogic where appropriate.Marcelina Kościelnicka2021-03-302-3/+10
| | | | See #2713.
* verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
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* abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-292-11/+62
| | | | | | | | | * abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests
* abc9: fix SCC issues (#2694)Eddie Hung2021-03-299-45/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
* Bump versionMarcelina Kościelnicka2021-03-301-1/+1
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* preproc: Fix up conditional handling.Marcelina Kościelnicka2021-03-301-3/+17
| | | | | Fixes #2710. Fixes #2711.
* gha: trim macOS dependenciesZachary Snow2021-03-281-3/+1
| | | | | | - Only install needed dependencies rather than using Brewfile - Remove brew update (recent enough formulae already baked in) - Saves ~16 minutes in macOS CI
* gha: combine jobs using matrixZachary Snow2021-03-281-43/+24
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* rtlil: add const accessors for modules, wires, and cellsZachary Snow2021-03-252-0/+15
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* Merge pull request #2702 from modwizcode/patch-1whitequark2021-03-241-0/+2
|\ | | | | Clarify bugpoint documentation regarding output
| * Clarify bugpoint documentation regarding outputIris Johnson2021-03-241-0/+2
|/ | | | | | | Bugpoint's current documentation does specify that the result of a run is stored as the current design, however it's easy to skim over what that means in practice. Add a documentation comment to explain specifically that an after bugpoint `write_xyz` pass is required to save the reduced design.
* ast: make design available to process_module()Zachary Snow2021-03-241-8/+8
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* rtlil: Fix process memwr roundtrip.Marcelina Kościelnicka2021-03-231-1/+1
| | | | Fixes #2646 fallout.
* Merge pull request #2696 from nakengelhardt/guidelinesN. Engelhardt2021-03-2311-318/+295
|\ | | | | split CodingReadme into multiple files
| * split CodingReadme into multiple filesN. Engelhardt2021-03-2211-318/+295
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* | quicklogic: Add .gitignore file for test outputs.Marcelina Kościelnicka2021-03-231-0/+4
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* | json: Improve the "processes in module" message a bit.Marcelina Kościelnicka2021-03-231-1/+1
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* verilog: check entire user type stack for type definitionXiretza2021-03-212-6/+22
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* sv: allow typenames as function return typesZachary Snow2021-03-193-0/+46
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* Merge pull request #2681 from msinger/fix-issue2606Miodrag Milanović2021-03-191-3/+23
|\ | | | | Fix check for bad std::regex
| * Fix check for bad std::regex (fixes #2606)Michael Singer2021-03-171-3/+23
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* | verilog: rebuild user_type_stack from globals before parsing fileXiretza2021-03-181-5/+21
| | | | | | | | | | | | | | | | | | | | | | | | This was actually a ticking UB bomb: after running the parser, the type maps contain pointers to children of the current AST, which is recursively deleted after the pass has executed. This leaves the pointers in user_type_stack dangling, which just happened to never be a problem due to another bug that causes typedefs from higher-level type maps to never be considered. Rebuilding the type stack from the design's globals ensures the AstNode pointers are valid.
* | Add simple CI using github actions.Marcelina Kościelnicka2021-03-181-0/+87
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