| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | | cxxrtl: preserve interior memory pointers across reset. | Catherine | 2021-12-11 | 2 | -95/+67 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, values, wires, and memories with an initializer were value-initialized in emitted C++ code. After this commit, all values, wires, and memories are default-initialized, and the default constructor of generated modules calls the reset() method, which assigns the members that have an initializer. | |||||
| | * | | | cxxrtl: use unique_ptr<value<>[]> to store memory contents. | whitequark | 2021-12-11 | 1 | -16/+16 | |
| | | | | | | | | | | | | | | | | | This makes the depth properly immutable. | |||||
| * | | | | Bump version | github-actions[bot] | 2021-12-12 | 1 | -1/+1 | |
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| * | | | | Fix unused param warning with ENABLE_NDEBUG. | Marcelina Kościelnicka | 2021-12-12 | 1 | -1/+1 | |
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| * | | | | rtlil: Dump empty connections when whole module is selected. | Marcelina Kościelnicka | 2021-12-12 | 1 | -2/+2 | |
| | | | | | | | | | | | | | | | | | | | | | Without this, empty connections will be always skipped by `dump`, since they contain no selected wires. This makes debugging rather confusing. | |||||
| * | | | | Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values | Catherine | 2021-12-11 | 1 | -1/+2 | |
| |\ \ \ \ | |/ / / |/| | | | write_verilog: dump zero width sigspecs correctly | |||||
| | * | | | write_verilog: dump zero width sigspecs correctly. | whitequark | 2021-12-11 | 1 | -1/+2 | |
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, zero width sigspecs were dumped as "" (empty string). Unfortunately, 1364-2005 5.2.3.3 indicates that an empty string is equivalent to "\0", and is 8 bits wide, so that's wrong. After this commit, a replication operation with a count of zero is used instead, which is explicitly permitted per 1364-2005 5.1.14, and is defined to have size zero. (Its operand has to have a non-zero size for it to be legal, though.) PR #1203 has addressed this issue before, but in an incomplete way. | |||||
| * | | | Bump version | github-actions[bot] | 2021-12-11 | 1 | -1/+1 | |
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| * | | | Merge pull request #3102 from YosysHQ/claire/enumxz | Miodrag Milanović | 2021-12-10 | 1 | -1/+1 | |
| |\ \ \ | | | | | | | | | Fix verific import of enum values with x and/or z | |||||
| | * | | | Fix verific import of enum values with x and/or z | Claire Xenia Wolf | 2021-12-10 | 1 | -1/+1 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | | | | Merge pull request #3097 from YosysHQ/modport | Miodrag Milanović | 2021-12-10 | 1 | -2/+12 | |
| |\ \ \ \ | |/ / / |/| | | | If direction NONE use that from first bit | |||||
| | * | | | Update verific.cc | Claire Xen | 2021-12-10 | 1 | -4/+7 | |
| | | | | | | | | | | | | | Ad-hoc fixes/improvements | |||||
| | * | | | If direction NONE use that from first bit | Miodrag Milanovic | 2021-12-08 | 1 | -0/+7 | |
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| * | | | | Merge pull request #3099 from YosysHQ/claire/readargs | Claire Xen | 2021-12-10 | 9 | -41/+52 | |
| |\ \ \ \ | | | | | | | | | | | Use "read" command to parse HDL files from Yosys command-line | |||||
| | * | | | | Fix the tests we just broke | Claire Xenia Wolf | 2021-12-10 | 6 | -10/+10 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| | * | | | | Added "yosys -r <topmodule>" | Claire Xenia Wolf | 2021-12-10 | 3 | -28/+35 | |
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| | * | | | | Use "read" command to parse HDL files from Yosys command-line | Claire Xenia Wolf | 2021-12-09 | 1 | -4/+8 | |
| |/ / / / | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | |||||
| * | | | | Bump version | github-actions[bot] | 2021-12-09 | 1 | -1/+1 | |
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| * | | | | opt_mem_priority: Fix non-ascii char in help message. | Marcelina Kościelnicka | 2021-12-09 | 2 | -12/+2 | |
| |/ / / | | | | | | | | | | This is a fixed version of #3072. | |||||
| * | | | Bump version | github-actions[bot] | 2021-12-04 | 1 | -1/+1 | |
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| * | | | Next dev cycle | Miodrag Milanovic | 2021-12-03 | 2 | -2/+5 | |
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| * | | | Release version 0.12 | Miodrag Milanovic | 2021-12-03 | 2 | -3/+3 | |
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| * | | | Update manual | Miodrag Milanovic | 2021-12-03 | 1 | -22/+181 | |
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| * | | | Add gitignore for gatemate | Miodrag Milanovic | 2021-12-03 | 1 | -0/+4 | |
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| * | | | Make sure cell names are unique for wide operators | Miodrag Milanovic | 2021-12-03 | 1 | -2/+2 | |
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| * | | | Bump version | github-actions[bot] | 2021-12-02 | 1 | -1/+1 | |
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| * | | | Update CHANGELOG and CODEOWNERS | Miodrag Milanovic | 2021-12-01 | 2 | -0/+22 | |
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| * | | | Bump version | github-actions[bot] | 2021-11-26 | 1 | -1/+1 | |
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| * | | | intel_alm: preliminary Arria V support | Lofty | 2021-11-25 | 6 | -7/+199 | |
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| * | | | sta: very crude static timing analysis pass | Lofty | 2021-11-25 | 9 | -62/+502 | |
| | | | | | | | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com> | |||||
| * | | | Bump version | github-actions[bot] | 2021-11-18 | 1 | -1/+1 | |
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| * | | | Merge pull request #3080 from YosysHQ/micko/init_wire | Miodrag Milanović | 2021-11-17 | 1 | -4/+6 | |
| |\ \ \ | | | | | | | | | Give initial wire unique ID, fixes #2914 | |||||
| | * | | | Give initial wire unique ID, fixes #2914 | Miodrag Milanovic | 2021-11-17 | 1 | -4/+6 | |
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| * | | | Bump version | github-actions[bot] | 2021-11-17 | 1 | -1/+1 | |
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| * | | | Support parameters using struct as a wiretype (#3050) | Kamil Rakoczy | 2021-11-16 | 2 | -7/+74 | |
| | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | |||||
| * | | | Bump version | github-actions[bot] | 2021-11-14 | 1 | -1/+1 | |
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| * | | | synth_gatemate Revert cascade A/B port mixup | Patrick Urban | 2021-11-13 | 2 | -12/+4 | |
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| * | | | synth_gatemate: Remove iob_map invokation | Patrick Urban | 2021-11-13 | 1 | -1/+0 | |
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| * | | | synth_gatemate: Add block RAM cascade support | Patrick Urban | 2021-11-13 | 2 | -112/+96 | |
| | | | | | | | | | | | | | | | | * add simulation model for block RAM cascade in 40K mode * limit 20K_SDP and 40K_SDP to 40 and 80 bits (the only useful configurations) | |||||
| * | | | synth_gatemate: Remove obsolete iob_map | Patrick Urban | 2021-11-13 | 3 | -61/+2 | |
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| * | | | synth_gatemate: Update pass | Patrick Urban | 2021-11-13 | 2 | -69/+33 | |
| | | | | | | | | | | | | | | | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style | |||||
| * | | | synth_gatemate: Remove specify blocks | Patrick Urban | 2021-11-13 | 1 | -92/+0 | |
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| * | | | synth_gatemate: Remove gatemate_bramopt pass | Patrick Urban | 2021-11-13 | 3 | -148/+0 | |
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| * | | | synth_gatemate: Apply new test practice with assert-max | Patrick Urban | 2021-11-13 | 7 | -12/+12 | |
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| * | | | synth_gatemate: Fix fsm test | Patrick Urban | 2021-11-13 | 1 | -2/+2 | |
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| * | | | synth_gatemate: Revise block RAM read modes and initialization | Patrick Urban | 2021-11-13 | 3 | -71/+230 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | * enable mixed read-width / write-width ports in SDP mode * fix NO_CHANGE and WRITE_THROUGH behavior during read access * remove redundant zero-initialization * set A/B_WE bit during map (gatemate_bramopt pass could be removed later) * differentiate "upper" and "lower" initialization for cascade mode | |||||
| * | | | synth_gatemate: Remove unsupported FF initialization | Patrick Urban | 2021-11-13 | 1 | -2/+0 | |
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| * | | | synth_gatemate: Rename multiplier factor parameters | Patrick Urban | 2021-11-13 | 1 | -13/+10 | |
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| * | | | synth_gatemate: Registers are uninitialized | Patrick Urban | 2021-11-13 | 2 | -3/+3 | |
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| * | | | Allow initial blocks to be disabled during tests | Patrick Urban | 2021-11-13 | 6 | -4/+20 | |
| | | | | | | | | | | | | | Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail. | |||||
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index : iCE40/yosys | |
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