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| | | | * | | | | | | Check for MULT18X18D, since that is working nowMiodrag Milanovic2019-10-042-14/+11
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| | | | * | | | | | | Check flops one by oneMiodrag Milanovic2019-10-044-71/+50
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| | | | * | | | | | | Removed alu and div_mod tests as agreedMiodrag Milanovic2019-10-044-57/+0
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| | | | * | | | | | | equiv_opt with -assertEddie Hung2019-09-301-3/+1
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| | | | * | | | | | | Update resource count for alu.ysEddie Hung2019-09-301-3/+3
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| | | | * | | | | | | Move $x to end as per 7f0eec8Eddie Hung2019-09-301-1/+1
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| | | | * | | | | | | Update fsm.ys resource countEddie Hung2019-09-301-3/+3
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| | | | * | | | | | | Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys ↵Eddie Hung2019-09-3037-0/+801
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| | | | | * | | | | | | Add comment to dpram test about related issue.SergeyDegtyar2019-09-181-0/+1
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| | | | | * | | | | | | adffs test update (equiv_opt -multiclock). div_mod test fixSergeyDegtyar2019-09-173-17/+12
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| | | | | * | | | | | | Remove stat command form shifter.ys testSergeyDegtyar2019-09-041-1/+1
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| | | | | * | | | | | | Fix ecp5 testsSergeyDegtyar2019-09-0411-2421/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5;
| | | | | * | | | | | | Uncomment sat command in memory.ys test.SergeyDegtyar2019-09-031-2/+1
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| | | | | * | | | | | | Add tests for ECP5 architectureSergeyDegtyar2019-09-0340-0/+3201
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| | | | | | * | | | | | hierarchy - proc reorderMiodrag Milanovic2019-10-184-9/+10
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| | | | | | * | | | | | Cleanup and formatingMiodrag Milanovic2019-10-044-2/+4
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| | | | | | * | | | | | split latches into separate checksMiodrag Milanovic2019-10-042-41/+24
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| | | | | | * | | | | | check muxes per typeMiodrag Milanovic2019-10-042-42/+37
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| | | | | | * | | | | | check ff's separatelyMiodrag Milanovic2019-10-042-26/+14
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| | | | | | * | | | | | Cleanup top modules and not used definesMiodrag Milanovic2019-10-045-44/+5
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| | | | | | * | | | | | remove alu testMiodrag Milanovic2019-10-042-36/+0
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| | | | | | * | | | | | Merge branch 'SergeyDegtyar/anlogic' of ↵Miodrag Milanovic2019-10-0423-0/+536
| |_|_|_|_|/| | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/SergeyDegtyar/yosys into mmicko/anlogic
| | | | | | * | | | | | Merge branch 'master' into SergeyDegtyar/anlogicSergey2019-10-01126-1686/+30035
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| | | | | | * | | | | | | run-test.sh Move $x at end of line.Sergey2019-10-011-1/+1
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| | | | | | * | | | | | | Add new tests for Anlogic architectureSergeyDegtyar2019-09-2323-0/+536
| | | | | |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present.
| | | | | | | * | | | | hierarchy - proc reorderMiodrag Milanovic2019-10-186-13/+15
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| | | | | | | * | | | | FF should be initialized to 0Miodrag Milanovic2019-10-041-1/+3
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| | | | | | | * | | | | Split mux tests per typeMiodrag Milanovic2019-10-042-38/+36
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| | | | | | | * | | | | Split latch checkMiodrag Milanovic2019-10-042-45/+24
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| | | | | | | * | | | | Add missing latch mappingMiodrag Milanovic2019-10-041-0/+12
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| | | | | | | * | | | | split rest od ff'sMiodrag Milanovic2019-10-043-30/+17
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| | | | | | | * | | | | Separate check for ff's typesMiodrag Milanovic2019-10-042-47/+48
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| | | | | | | * | | | | Cleaned testsMiodrag Milanovic2019-10-045-49/+4
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| | | | | | | * | | | | Remove not needed testsMiodrag Milanovic2019-10-046-75/+0
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| | | | | | | * | | | | Merge branch 'SergeyDegtyar/efinix' of ↵Miodrag Milanovic2019-10-0431-0/+710
| |_|_|_|_|_|/| | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://github.com/SergeyDegtyar/yosys into mmicko/efinix
| | | | | | | * | | | | run-test.sh Move $x at end of line.Sergey2019-10-011-1/+1
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| | | | | | | * | | | | Merge branch 'master' into SergeyDegtyar/efinixSergey2019-10-01126-1686/+30035
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| | | | | | | * | | | | Add new tests for Efinix architecture.SergeyDegtyar2019-09-2331-0/+710
| | | | | | |/ / / / / | | | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail.
* | | | | | | | | | | Change smtbmc "Warmup failed" status to "PREUNSAT"Clifford Wolf2019-10-031-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | Update ABC to git rev 623b5e8Clifford Wolf2019-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | Bump versionClifford Wolf2019-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | | | | | Merge pull request #1419 from YosysHQ/eddie/lazy_deriveClifford Wolf2019-10-032-35/+59
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | module->derive() to be lazy and not touch ast if already derived
| * | | | | | | | | | | Fix for svinterfacesEddie Hung2019-09-301-2/+8
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| * | | | | | | | | | | module->derive() to be lazy and not touch ast if already derivedEddie Hung2019-09-302-33/+51
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* | | | | | | | | | | Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-032-6/+50
|\ \ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Add -select option to aigmap
| * | | | | | | | | | | Add quick testEddie Hung2019-09-301-0/+10
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| * | | | | | | | | | | Add -select option to aigmapEddie Hung2019-09-301-6/+40
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* | | | | | | | | | | Merge pull request #1429 from YosysHQ/clifford/checkmappedClifford Wolf2019-10-032-27/+56
|\ \ \ \ \ \ \ \ \ \ \ | |_|_|_|_|/ / / / / / |/| | | | | | | | | | Add "check -mapped"
| * | | | | | | | | | Add "check -allow-tbuf"Clifford Wolf2019-10-031-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | | | | | | Add "check -mapped"Clifford Wolf2019-10-022-21/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 14:01:57 +0000