aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * | Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-122-27/+58
| | |
| * | Fixed hashlib for 64 bit int keysClifford Wolf2015-08-121-3/+9
| | |
| * | Added SMV back-end 'test_cells.sh' scriptClifford Wolf2015-08-121-0/+33
| | |
* | | More ASCII encoding fixesClifford Wolf2015-08-132-2/+2
| | |
* | | Fixed CRLF line endingsClifford Wolf2015-08-136-563/+563
| | |
* | | Some ASCII encoding fixes (comments and docs) by Larry DoolittleClifford Wolf2015-08-134-6/+6
|/ /
* | Merge pull request #70 from gaomy3832/bugfixClifford Wolf2015-08-121-0/+10
|\ \ | | | | | | Remove unused blackbox modules in opt_clean.
| * | Remove unused blackbox modules in opt_clean.Mingyu Gao2015-08-111-0/+10
| | |
| * | Bugfix for cell hash cache option in opt_share.Mingyu Gao2015-08-101-0/+2
| | |
* | | Bugfix for cell hash cache option in opt_share.Mingyu Gao2015-08-111-0/+2
| | |
* | | Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-112-2/+11
| | |
* | | Added missing ct_all setup to opt_cleanClifford Wolf2015-08-111-0/+3
|/ /
* | Use MEMID as name for $mem cellClifford Wolf2015-08-092-43/+53
| |
* | Merge pull request #69 from zeldin/masterClifford Wolf2015-08-071-0/+10
|\ \ | | | | | | Added iCE40 WARMBOOT cell
| * | Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-061-0/+10
|/ /
* | Remove some very strange whitespace in btor.cc (by Larry Doolittle)Clifford Wolf2015-08-051-7/+7
| |
* | Bugfix in SMV back-end for partially unassigned wiresClifford Wolf2015-08-051-4/+16
| |
* | Added ENABLE_LIBYOSYS Makefile optionClifford Wolf2015-08-042-14/+10
| |
* | Added $assert support to SMV back-endClifford Wolf2015-08-041-4/+21
| |
* | Added libyosys.so buildClifford Wolf2015-08-043-3/+24
| |
* | Merge pull request #68 from zeldin/masterClifford Wolf2015-08-011-1/+8
|\ \ | | | | | | Add -noautowire option to verilog frontend
| * | Add -noautowire option to verilog frontendMarcus Comstedt2015-08-011-1/+8
|/ /
* | Added WORDS parameter to $meminitClifford Wolf2015-07-316-16/+95
| |
* | Fixed flatten $meminit handlingClifford Wolf2015-07-301-1/+1
| |
* | Improvements in BLIF back-endClifford Wolf2015-07-291-5/+84
| |
* | Fixed nested mem2regClifford Wolf2015-07-292-4/+11
| |
* | Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-271-1/+0
| |
* | Fixed "check" command for inout portsClifford Wolf2015-07-271-3/+11
| |
* | Some cleanups in opt_rmdffClifford Wolf2015-07-251-16/+9
| |
* | Added "miter -assert"Clifford Wolf2015-07-251-1/+93
| |
* | Keep modules with $assume (like $assert)Clifford Wolf2015-07-251-1/+1
| |
* | Improved $adff simplificationClifford Wolf2015-07-241-1/+1
| |
* | iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-201-20/+43
| |
* | Fixed techmap processes error msgClifford Wolf2015-07-181-2/+3
| |
* | Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-181-0/+2
| |
* | Some fixes in "select" commandClifford Wolf2015-07-161-1/+3
| |
* | Fixed YosysJS.create_worker() usage of this.url_prefixClifford Wolf2015-07-101-1/+1
| |
* | Improved liberty file test caseClifford Wolf2015-07-061-1/+2
| |
* | Updated ABCClifford Wolf2015-07-061-1/+1
| |
* | Do not collect disabled $memwr cellsClifford Wolf2015-07-061-15/+18
| |
* | Improved YosysJS WebWorker APIClifford Wolf2015-07-043-10/+51
| |
* | Bugfix in fsm_extractClifford Wolf2015-07-031-3/+16
| |
* | Added "synth -nofsm"Clifford Wolf2015-07-021-1/+10
| |
* | Fixed trailing whitespacesClifford Wolf2015-07-02195-729/+729
| |
* | Added opt_const -clkinvClifford Wolf2015-07-012-6/+95
| |
* | Added logic-loop error handling to freduceClifford Wolf2015-06-301-0/+11
| |
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-06-303-33/+145
|\ \
| * | Added YosysJS.create_worker()Clifford Wolf2015-06-283-33/+145
| | |
* | | Bugfix in chparamClifford Wolf2015-06-301-6/+5
| | |
* | | Added design->rename(module, new_name)Clifford Wolf2015-06-303-3/+9
|/ /