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| | * | | | | | | | | Merge pull request #1253 from YosysHQ/clifford/checkClifford Wolf2019-08-073-9/+17
| | |\ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Be less aggressive with running design->check()
| | | * | | | | | | | | Be less aggressive with running design->check()Clifford Wolf2019-08-063-9/+17
| | | |/ / / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | | Merge pull request #1257 from YosysHQ/clifford/cellcostsClifford Wolf2019-08-073-109/+103
| | |\ \ \ \ \ \ \ \ \ | | | |_|_|_|_|_|_|_|/ | | |/| | | | | | | | Redesign of cell cost API
| | | * | | | | | | | Tweak default gate costs, cleanup "stat -tech cmos"Clifford Wolf2019-08-072-20/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * | | | | | | | Redesign of cell cost APIClifford Wolf2019-08-072-93/+97
| | | | |_|_|_|_|_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | Update CHANGELOGDavid Shah2019-08-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | | Merge pull request #1241 from YosysHQ/clifford/jsonfixDavid Shah2019-08-072-36/+71
| | |\ \ \ \ \ \ \ \ | | | |/ / / / / / / | | |/| | | | | | | Improved JSON attr/param encoding
| | | * | | | | | | Update JSON front-end to process new attr/param encodingClifford Wolf2019-08-011-23/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | * | | | | | | Implement improved JSON attr/param encodingClifford Wolf2019-08-011-13/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | | | Merge pull request #1232 from YosysHQ/dave/write_gzipDavid Shah2019-08-064-7/+79
| | |\ \ \ \ \ \ \ \ | | | |_|/ / / / / / | | |/| | | | | | | Add support for writing gzip-compressed files
| | | * | | | | | | Add test for writing gzip-compressed filesDavid Shah2019-08-062-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | | * | | | | | | Add support for writing gzip-compressed filesDavid Shah2019-08-062-7/+61
| | |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * | | | | | | Merge pull request #1251 from YosysHQ/clifford/nmuxClifford Wolf2019-08-0619-42/+174
| | |\ \ \ \ \ \ \ | | | |_|/ / / / / | | |/| | | | | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
| | | * | | | | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-0619-42/+174
| | |/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | | | Merge pull request #1242 from jfng/fix-proc_prune-partialwhitequark2019-08-031-2/+11
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | proc_prune: Promote partially redundant assignments.
| | | * | | | | | proc_prune: Promote partially redundant assignments.Jean-François Nguyen2019-08-011-2/+11
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| | * | | | | | Merge pull request #1238 from mmicko/vsbuild_fixClifford Wolf2019-08-022-1/+2
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Visual Studio build fix
| | | * | | | | | Visual Studio build fixMiodrag Milanovic2019-07-312-1/+2
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| | * | | | | | Merge pull request #1239 from mmicko/mingw_fixClifford Wolf2019-08-0211-25/+37
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | Fix formatting for msys2 mingw build
| | | * | | | | | Fix linking issue for new mxe and pthreadMiodrag Milanovic2019-08-011-1/+2
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| | | * | | | | | Fix yosys linking for mxeMiodrag Milanovic2019-08-011-1/+1
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| | | * | | | | | New mxe hacks needed to support 2ca237eMiodrag Milanovic2019-08-011-0/+4
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| | | * | | | | | Fix formatting for msys2 mingw build using GetSizeMiodrag Milanovic2019-08-0110-23/+30
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| * | | | | | | Do not pack registers if (* keep *)Eddie Hung2019-08-071-0/+20
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* | | | | | | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | DSP48E1 sim model: Comb, no pre-adder, mode workingDavid Shah2019-08-082-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | [wip] sim model testingDavid Shah2019-08-084-15/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | [wip] sim model testingDavid Shah2019-08-083-40/+360
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-071-6/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-23/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | | [wip] DSP48E1 sim model improvementsDavid Shah2019-08-061-8/+75
|/ / / / / / / | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | | | | Add comment about supporting $dffe in ice40_dspEddie Hung2019-08-011-0/+1
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* | | | | | | Pack P register properlyEddie Hung2019-08-011-2/+4
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* | | | | | | Trim Y_WIDTHEddie Hung2019-08-011-5/+3
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* | | | | | | Add DSP_SIGNEDONLY backEddie Hung2019-08-011-0/+16
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* | | | | | | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTHEddie Hung2019-08-012-5/+12
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* | | | | | | Change $__softmul back to $mulEddie Hung2019-08-011-0/+1
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* | | | | | | Cope with sign extension in mul2dspEddie Hung2019-08-012-14/+14
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* | | | | | | Revert "Do not do sign extension in techmap; let packer do it"Eddie Hung2019-08-011-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 595a8f032f1e9db385959f92a4a414a40de291fd.
* | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-0125-86/+219
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| * | | | | | Merge pull request #1236 from YosysHQ/eddie/xc6s_brams_mapEddie Hung2019-08-011-3/+3
| |\ \ \ \ \ \ | | |_|/ / / / | |/| | | | | xc6s_brams_map.v: RST -> RSTBRST for RAMB8BWER
| | * | | | | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
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| * | | | | Merge pull request #1233 from YosysHQ/clifford/deferClifford Wolf2019-07-312-49/+21
| |\ \ \ \ \ | | |/ / / / | |/| | | | Call "read_verilog" with -defer from "read"
| | * | | | Update README to use "read" instead of "read_verilog"Clifford Wolf2019-07-291-48/+19
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | | | Call "read_verilog" with -defer from "read"Clifford Wolf2019-07-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Merge pull request #1228 from YosysHQ/dave/yy_buf_sizeEddie Hung2019-07-291-0/+3
| |\ \ \ \ \ | | | | | | | | | | | | | | verilog_lexer: Increase YY_BUF_SIZE to 65536
| | * | | | | verilog_lexer: Increase YY_BUF_SIZE to 65536David Shah2019-07-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-17 05:35:26 +0000